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 Verilog-A Monte-Carlo simulations 

Last post Fri, Nov 23 2012 8:31 AM by Andrew Beckett. 1 replies.
Started by eppo 22 Nov 2012 06:17 AM. Topic has 1 replies and 735 views
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  • Thu, Nov 22 2012 6:17 AM

    • eppo
    • Not Ranked
    • Joined on Tue, Jun 29 2010
    • Posts 14
    • Points 300
    Verilog-A Monte-Carlo simulations Reply

     Hi all,

     I would like to performe Monte-Carlo simulations by using my own transistor model developped in verilog-A language.

     For this, I added the line below in the code in order to vary the parameter "CMC" (CMC is a new parameter)

    (*cds_inherited_parameter*) parameter real CMC=0.0;  

    also in the file.scs I have added the sequence below :

      parameters CMC

    statistics {
       mismatch {
          vary CMC dist=gauss std=0.001a
          }
          }

     When i try to run simulation i have the following errors :

    ERROR (SFE-3): `BMA_MODEL' is being redefined.

    WARNING (SFE-30): "input.scs" 15: I1: `CMC' is not a valid parameter for an instance of `BMA_MODEL'.  Ignored

    ERROR (SFE-1997): "input.scs" 15: I1: parameter `CMC': Unknown parameter name `CMC' found in expression.  

    I guess the procedure that I use is wrong. How can I introduce variations of parameters model and then running Monte-carlo simulation?

    Thanks, 

    • Post Points: 20
  • Fri, Nov 23 2012 8:31 AM

    Re: Verilog-A Monte-Carlo simulations Reply

    The error suggests that BMA_MODEL is defined more than once. The warning then suggests that whatever BMA_MODEL you have, it does not have a parameter CMC. And the last error is probably because no value is defined for CMC on the parameters statement.

    It's really hard to tell without seeing your complete setup. If you can't provide that here, I'd suggest logging a service request.

    Regards,

    Andrew.

    • Post Points: 5
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Started by eppo at 22 Nov 2012 06:17 AM. Topic has 1 replies.