I wonder if others have solutions for reading netlists containing "SEQGEN" generic registers into LEC? If I read an RTL design into "another synthesis tool" and write out the netlist before technology mapping, the registers are implemented with these generic flip-flops.
Any tricks to deal with this? Is there a SEQGEN Verilog model available, for example? I know I could run mapping in the synthesis tool, but then you're not strictly verifying the pre-mapping netlist.
Originally posted in cdnusers.org by firstname.lastname@example.org