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 How to connect vPlan and your testbench 

Last post Thu, Nov 22 2012 5:51 PM by jefflieu. 6 replies.
Started by jefflieu 20 Nov 2012 01:36 AM. Topic has 6 replies and 1625 views
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  • Tue, Nov 20 2012 1:36 AM

    • jefflieu
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    • Joined on Mon, Nov 7 2011
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    • Points 65
    How to connect vPlan and your testbench Reply

     Hi guys,

    I've been exploring with the labs in UVM-SystemVerilog Workshop. The lab 1 to 5 are good, but lab 6 is sort of useless. It only shows me how to view the prewritten sessions and vplan. In the end, I don't know how to create the vPlan map the plan to the testbench so that it can automatically measure my verification progress. 

    I don't why the lab 6 isn't built up from lab 5 which it should.  

    Is there any other lab/document that I can follow? 

    I search all over the earth and understand roughly that : you have a spec, then you create your vplan. Your vplan can map to your spec and your vplan can map to your testbench to measure the progress of your verification. I just don't know how to "connect" vplan to my testbench. 

    Thanks a lot for reading

     Jeff

     

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    • Post Points: 20
  • Tue, Nov 20 2012 2:21 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
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    Re: How to annotate between vPlan and your testbench Reply

    Hello Jeff.

    Thanks for the feedback on the labs. I think the UVM ones try not to distract you too much from the core UVM content, which is why the final MDV section is quite thin. However the SoC Verification Kit shipped with Incisive does have a lot more workshops. If you take a peek at the  dedicated MDV workshops you should find a much more detailed set of labs for building your own vPlan, based on the same design.

     I'm not sure how you navigated to the contect for the UVM workshop but assuming no prior knowledge of the tools...

    Open "cdnshelp" from the Linux prompt, then search for "MDV Planning Workshop". Alternatively open the "Incisive Verification Kits" chapter in cdnshelp's hierarchy pane, then go into "Getting Started" followed by "Kit Workshop Content".

    Hope that helps, and please do give us more feedback :) 

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
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    • Post Points: 20
  • Tue, Nov 20 2012 5:41 PM

    • jefflieu
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    Re: How to annotate between vPlan and your testbench Reply

     Thanks Steve!

    I'm trying that out. There are just too many documents and topics. With your hint, it's much easier. 

    Jeff

    • Post Points: 5
  • Tue, Nov 20 2012 11:55 PM

    • jefflieu
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    Re: How to annotate between vPlan and your testbench Reply
    Hi,

    Sorry. I can't do much with the workshop

    I'm attempting to create sessions, by following the Instrastructure workshop of MVD foundations series.

    I receive nothing like described.I'm supposed to see "Hello World" printed. My session is always failed.

    Here's my screen:

    Any advice?

    Btw, what's session? Is it script to run multiple/regression test?

    I guess I haven't understood the "concept" behind emanager, vplan, and the testbench. How are they linked and work together?

    I'll appreciate it if you could point me to some documents. Is there any explanatory video for the presentation slide?

    Thank you!

    Jeff


    p.s Sorry if I asked dumb questions, quite a noob and lost by the bunch of documents from cdnshelp.
    • Post Points: 35
  • Thu, Nov 22 2012 9:15 AM

    • StephenH
    • Top 25 Contributor
    • Joined on Tue, Sep 2 2008
    • Bristol, Avon
    • Posts 277
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    Re: How to annotate between vPlan and your testbench Reply

    Jeff, no such thing as a dumb question! :-)

    Unfortunately your pictures didn't come through so I can't tell what the problem is. You might try asking your local Cadence AE to help get you started (I'm not sure where you are because you didn't fill in your profile).

    There are some introductory videos in the Kit. Navigate in cdnshelp to "Incisive Verification Kits - Getting Started". Under there you have "Kit Workshop Content" followed by "Video Content". These will require you to have Flash player enabled on your Linux machine, or you can access the same docs on your PC via the Cadence web site http://support.cadence.com/.

    Specifically you want the Metric Drivern Verification video, this will talk you through all the concepts. 

    Hope this helps. 

    Steve Hobbs / Applications Engineer / Cadence Functional Verification
    • Post Points: 5
  • Thu, Nov 22 2012 9:23 AM

    • pcarzola
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    Re: How to annotate between vPlan and your testbench Reply

    Jeff,

    Please send me an email to pcarzola@cadence.com with your screenshots. We'll see if we can help you further.

    The workshop is the best place to get started but you'll need to make sure you follow all the setup instructions it mentions.

    -Paul

     

    • Post Points: 20
  • Thu, Nov 22 2012 5:51 PM

    • jefflieu
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    Re: How to connect vPlan and your testbench Reply

    Here's the screenshot. Somehow I can't insert it to the post :(

    https://docs.google.com/open?id=0B8ZL9wN9Gn7lOGNLQUM1N1duc28

    Really appreciate your attention. :)

    • Post Points: 5
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Started by jefflieu at 20 Nov 2012 01:36 AM. Topic has 6 replies.