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 Z axis clearance constraint for High voltage nets 

Last post Tue, Nov 20 2012 4:28 AM by Robyd. 4 replies.
Started by Robyd 19 Nov 2012 07:34 AM. Topic has 4 replies and 1084 views
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  • Mon, Nov 19 2012 7:34 AM

    • Robyd
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    • Rehovot, Israel
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    Z axis clearance constraint for High voltage nets Reply

    Hello

    Is there any way to insert a clearance constraint to avoid high voltage clearance violation  between different layers.

    As i see it must take into acount the layer stackup dielectric thicknesses and make angular geometric clearance calculation between different objects in different layers ?

    Maybe any body uses a custom SKILL for that ?

    Thank you 

    • Post Points: 20
  • Mon, Nov 19 2012 10:34 AM

    • TH Designs
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    Re: Z axis clearance constraint for High voltage nets Reply

    What kind of voltages are we talking about? You may just have to find out what the dielectric withstand voltage of the pcb/prepreg material your are using is and adjust your board thickness / stackup accordingly.

    STD FR4 is rated at 20kV/mm. Other pcb material maufacturers may have higher rated products. (Rogers comes to mind).

    I know of no z-axis constraint other then identifying specific layers to route the high voltages on. Possibly alternate inner layers to increase the z-axis spacing.

    Tom

    • Post Points: 20
  • Mon, Nov 19 2012 12:03 PM

    • Robyd
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    Re: Z axis clearance constraint for High voltage nets Reply
    Tom

    For PCB layout we follow IPC 2221A Table 6-1, which provides  recommended minimum spacing between conductors - The clearances needed are much smaller .

    please see http://www.smpspowersupply.com/ipc2221pcbclearance.html

    In very Dense PCB's we have layer to layer separation of down to 3 mil.

    According to IPC table voltage difference higher than 50V in internal layers requires 4 mil clearance ( in adjacent layer)

    When we design with higher voltages we need to keep clearance from objects in different layers ( in any angle - in Z axis)  of the PCB.

     There are also other clearance requirments such as IPC9592 and UL60950

    See also additional info at http://www.smps.us/pcbtracespacing.html

     There a real need for Z axis clearance control for PCB that comply to IPC Requirments or UL .

     Roby
    • Post Points: 20
  • Mon, Nov 19 2012 6:00 PM

    • redwire
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    Re: Z axis clearance constraint for High voltage nets Reply

     You really need to control z-axis by your stackup.  Also, the IPC table does not apply to Z-axis spacing.  See the earlier post.

    UL 60950 latest edition will show you what the z-axis rules are.  They have *recently* changed.  If you run 3 cloths of pre-preg you can squeeze down.  There are also tests that can be done as proof of compliance that will supercede any printed "rules"

     50V spacing can *easily* be met by 2 mil spacing in z axis.  Talk to your fabricator about what they can test to.

    • Post Points: 20
  • Tue, Nov 20 2012 4:28 AM

    • Robyd
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    Re: Z axis clearance constraint for High voltage nets Reply

    redwire - thabk you for the reply

    in IPC-2221 paragraph 6.3   you can find requirment for Z Axis i Quote 

    "6.3 Electrical Clearance : Spacing between conductors on individual layers should be maximized whenever possible. The minimum spacing between conductors....... layer to layer conductive spaces (z=axis), and between conductive materials ... and conductors shall be in accordance with table 6-1,....."

     redwire :can you kindly share some examples of UL60950 clearance requirments fro PCB layout for Z axis ?

    I understand that Allegro does not support Z axis clearance constraints .

     

    About the 2 mil clearance being enough for 50V - this was only an example

    BUT sometimes i have up to 1500 v and higher

    roby 

     

    • Post Points: 5
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Started by Robyd at 19 Nov 2012 07:34 AM. Topic has 4 replies.