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 Cadence Encounter doesn't fix hold violations? 

Last post Tue, Nov 13 2012 1:31 AM by Kuxx. 0 replies.
Started by Kuxx 13 Nov 2012 01:31 AM. Topic has 0 replies and 1105 views
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  • Tue, Nov 13 2012 1:31 AM

    • Kuxx
    • Not Ranked
    • Joined on Tue, Mar 15 2011
    • Posts 1
    • Points 5
    Cadence Encounter doesn't fix hold violations? Reply
    Hi everyone,
    please help me with the next problem:

    I'm designing a digital IC based on FPGA-verified source code using Cadence tools: Encounter for P&R and optimization and Incisive simulator (NCSim may be the second name) for checking the resulting waveforms.
    After P&R, in post-route stage, I optimized design using the next commands:

    optDesign -postRoute
    optDesign -postRoute -hold

    and the results are:
    +--------------------+---------+---------+---------+---------+---------+---------+
    | Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    | WNS (ns):| -0.021 | -0.021 | 0.044 | N/A | N/A | N/A |
    | TNS (ns):| -1.751 | -1.751 | 0.000 | N/A | N/A | N/A |
    | Violating Paths:| 356 | 356 | 0 | N/A | N/A | N/A |
    | All Paths:|3.64e+05 |2.45e+05 |1.19e+05 | N/A | N/A | N/A |
    +--------------------+---------+---------+---------+---------+---------+---------+
    +--------------------+---------+---------+---------+---------+---------+---------+
    | Hold mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
    +--------------------+---------+---------+---------+---------+---------+---------+
    | WNS (ns):| 0.031 | 0.038 | 0.031 | N/A | N/A | N/A |
    | TNS (ns):| 0.000 | 0.000 | 0.000 | N/A | N/A | N/A |
    | Violating Paths:| 0 | 0 | 0 | N/A | N/A | N/A |
    | All Paths:|3.64e+05 |2.45e+05 |1.19e+05 | N/A | N/A | N/A |
    +--------------------+---------+---------+---------+---------+---------+---------+

    I know that setup violations were not fixed correctly, but hold were.
    After that, I extracted the resulting netlist and SDF file and annotated them to simulator, and there are more timing violations in it's log file, but only HOLD. I think that setup violations were fixed decreasing the clock frequency in testbench, but, of course, HOLD not.

    A part of ncsim.log file:
    Warning! Timing violation
    $setuphold<hold>( posedge CK &&& (ENABLE_RB === 1'b1):3236050 PS, negedge E &&& (ENABLE_RB === 1'b1):3236050 PS, 1.0 : 10 PS, 1.0 : 10 PS );
    File: ./uk65lscsp10bbrccs_sdf30.v, line = 33170
    Scope: :UUT.bis64.B_E.\tmp_reg[33] 
    Time: 3236050 PS


    Warning! Timing violation
    $setuphold<hold>( posedge CK &&& (ENABLE_RB === 1'b1):3236050 PS, negedge E &&& (ENABLE_RB === 1'b1):3236050 PS, 1.0 : 10 PS, 1.0 : 10 PS );
    File: ./uk65lscsp10bbrccs_sdf30.v, line = 33170
    Scope: :UUT.bis64.B_E.\tmp_reg[34] 
    Time: 3236050 PS

    How can I fix hold violations in encounter? What I need to do? Please note, the program says that there are no hold violations in design.

    Thanks in advance,
    Kuxx.
    • Post Points: 5
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Started by Kuxx at 13 Nov 2012 01:31 AM. Topic has 0 replies.