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 Schematic p-cell for modelling parasitic resistance and capacitance 

Last post Mon, Nov 26 2012 3:45 AM by tmart. 2 replies.
Started by tmart 06 Nov 2012 05:09 AM. Topic has 2 replies and 833 views
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  • Tue, Nov 6 2012 5:09 AM

    • tmart
    • Not Ranked
    • Joined on Fri, Feb 17 2012
    • Oslo, Oslo
    • Posts 7
    • Points 95
    Schematic p-cell for modelling parasitic resistance and capacitance Reply

    Hi, 

    I'm looking for a schematic p-cell which models parasitic resistance and capacitance in layout.

    A former employer of mine had this function; to model a metal wire or interconnect in the layout, you'd place a special p-cell in your schematic, enter in which metal layer it was placed, add length and width as well as surrounding density, and the p-cell would pop out with a calculated RC value and act as a lumped resistor and capacitor. This was incredibly efficient in pre-layout simulation of routing-sensitive modules.

    Is there built-in support in Cadence for such a function, or will I have to write a p-cell from scratch myself? 

    Best regards, 

    Tore

    • Post Points: 20
  • Sat, Nov 10 2012 8:13 AM

    Re: Schematic p-cell for modelling parasitic resistance and capacitance Reply

    I think you'd have to write this yourself.

    Andrew

    • Post Points: 20
  • Mon, Nov 26 2012 3:45 AM

    • tmart
    • Not Ranked
    • Joined on Fri, Feb 17 2012
    • Oslo, Oslo
    • Posts 7
    • Points 95
    Re: Schematic p-cell for modelling parasitic resistance and capacitance Reply

    Sorry about the late reply, I've been OOO. 

    That's a shame, but not completely unexpected. Thanks anyways,

    -T  

    • Post Points: 5
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Started by tmart at 06 Nov 2012 05:09 AM. Topic has 2 replies.