Hi Micro, Originally posted in cdnusers.org by makkarm
Technically, mapping is always 1 to 1! One DFF from golden can only map to One DFF on the revised. I am going to make two assumptions of what could be going on your design based on the question.
#1:Unfolded DLAT's in the revised:
You will need to use the command
SETUP> set flatten model -latch_fold
which will fold the master & slave latches in your design to DFF. This way the mapping happens cleanly
If you have multiple DFF's in the gate-level that need to match to a single DFF in the golden, then it is a case of register cloning. For such cases you need to specify all your multiple cloned registers, DFF's are equivalent, with the command
SETUP> add instance equivalent . . -revised This specifies DFF1, DFF2, DFF3 are all equivalent or cloned in the gate-level design. Therefore all three flops will automatically map to 1 DFF in the golden and hence achieving your "1-to-many" mapping scenario.
Once you have abstracted your transistor/spice level design, you can write out the resulting verilog with
SETUP> write design -verilog
Since I made some assumptions earlier, I will ask you contact sourcelink as they have experts who can debug the issues for you directly.