Home > Community > Forums > Logic Design > RTL Compiler synthesis commands for TDC design

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 RTL Compiler synthesis commands for TDC design 

Last post Thu, Nov 1 2012 9:06 AM by Maheshnb. 0 replies.
Started by Maheshnb 01 Nov 2012 09:06 AM. Topic has 0 replies.
Page 1 of 1 (1 items)
Sort Posts:

  • Thu, Nov 1 2012 9:06 AM

    • Maheshnb
    • Not Ranked
    • Joined on Thu, Nov 1 2012
    • Posts 5
    • Points 85
    RTL Compiler synthesis commands for TDC design Reply

    Greeting to all,

            I have written code for inverter chain which uses LVT and HVT cell to have slow and fast path for my vernier Time to digital converter......

    my  first quesrtion is

    is it possible to synthesize this from gpdk library from cadence??????

    if so please provide me the RTL compiler command list

     

    mahesh

    • Post Points: 5
Page 1 of 1 (1 items)
Sort Posts:
Started by Maheshnb at 01 Nov 2012 09:06 AM. Topic has 0 replies.