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 BUS in extracted view 

Last post Thu, Nov 1 2012 10:16 AM by Zdeno. 1 replies.
Started by Zdeno 30 Oct 2012 05:00 AM. Topic has 1 replies and 792 views
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  • Tue, Oct 30 2012 5:00 AM

    • Zdeno
    • Top 500 Contributor
    • Joined on Tue, Oct 12 2010
    • Geneve, Geneva
    • Posts 25
    • Points 290
    BUS in extracted view Reply

    Hello,

    I am simulating extracted view in ADEXL. I use OSS-based netlister to create netlist. Extracted view contains nets:

    cnf_reg_analog<15>

    cnf_reg_analog<14>

    ...

    cnf_reg_analog<3>

     

    I want to merge all nets to one bus as it is in my verilog netlist:

    output [15:3] cnf_reg_analog;

    but I got the message:

    WARNING (VLOGNET-186): Unable to generate explicit netlist for the 'z_chip_def/cell/extracted_rc' cell view because split buses and/or bundle terminals are present in it.

    Set the Terminal SyncUp option on the Netlist Setup form as 'Merge All' or set the hnlVerilogTermSyncUp variable as 'mergeAll' and netlist again.

    And netlist looks like:

    module cell (cnf_out, \cnf_reg_analog(15) , \cnf_reg_analog(14) ,

    \cnf_reg_analog(13) , \cnf_reg_analog(12) , \cnf_reg_analog(11) ,

    \cnf_reg_analog(10) , \cnf_reg_analog(9) , \cnf_reg_analog(8) ,

    \cnf_reg_analog(7) , \cnf_reg_analog(6) , \cnf_reg_analog(5) ,

    \cnf_reg_analog(4) , \cnf_reg_analog(3) , cnt_out, gnd, vdd, clk,

    clk_cnt, cnf_en, cnf_in, cnt_in, hit, rst, shutter);

    output cnf_out, \cnf_reg_analog(15) , \cnf_reg_analog(14) ,

    \cnf_reg_analog(13) , \cnf_reg_analog(12) , \cnf_reg_analog(11) ,

    \cnf_reg_analog(10) , \cnf_reg_analog(9) , \cnf_reg_analog(8) ,

    \cnf_reg_analog(7) , \cnf_reg_analog(6) , \cnf_reg_analog(5) ,

    \cnf_reg_analog(4) , \cnf_reg_analog(3) , cnt_out;


    I tried to set hnlVerilogTermSyncUp to 'mergeAll', also to 'honorSM' without any effect. I can not find even SyncUp option in Netlist Setup.

    I use:

    IC06.15.506-615, MMSIM10.11.200, INCISIV10.20.026

    Is there any solution how to create BUS from nets in extracted view?

    Thank you very much for the answer.

    Best Regards


    Zdeno

    • Post Points: 5
  • Thu, Nov 1 2012 10:16 AM

    • Zdeno
    • Top 500 Contributor
    • Joined on Tue, Oct 12 2010
    • Geneve, Geneva
    • Posts 25
    • Points 290
    Re: BUS in extracted view Reply

     Hi,

    no one has idea how to correct this problem? Still I can not plot signal from bus In ADEXL with following error:

    ERROR (WIA-1006): Unable to plot expression <VT("/cnf<3>" "/home/zdenko/simulation/z_chip_sim/cell/adexl/results/data/Interactive.143/psf/tran")>

    because it does not evaluate to an object that can be plotted, like a waveform or

    parametric wave. See the Visualization & Analysis Tool documentation for information

    about the types of objects that can be plotted in Visualization & Analysis Tool. Only

    the expressions that evaluate to those objects can be plotted.

    *Warning* Wave1 is not a waveform object that can be displayed and

    will be DELETED automatically.

    name: "/cnf<3>"

     

    Thanks a lot.

     

    Zdeno

     

    • Post Points: 5
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Started by Zdeno at 30 Oct 2012 05:00 AM. Topic has 1 replies.