I am using Cadence spectre/Virtuoso for my simulation. I have a "D" latch driven by clock adn whenever the clock is transiting from high to low or low to high, there is a glitch in the output. If i increase the rise time of my clock the glitch will reduce, but my friend using the same tool, same version, same inputs works completely fine for him( even at low rise time of clock, (without any glitch). I wonder what might be wrong in my circuit.
If i perform the post layout simulation of the same circuit it works fine, i have problem if i simulate my pre layout schematic. Please let me know if you need further info reg this.