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 irun: design.v is verilog and verilog AMS 

Last post Thu, Oct 18 2012 8:29 AM by moogyd. 2 replies.
Started by moogyd 18 Oct 2012 07:28 AM. Topic has 2 replies and 1528 views
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  • Thu, Oct 18 2012 7:28 AM

    • moogyd
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    irun: design.v is verilog and verilog AMS Reply

    Hi,

    We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue.

    We have a file design.v, containing module design. Depending on a define, this can either be a standard digital module, or a WREAL model.

    i.e. Within the file

    `ifdef WREAL

    wreal sig_name;

     `endif

    This issue is that irun uses the file extesion to infer the type of file, in this case, it does not work.

    This is a non-trivial design, so I have multiple verilog, vhdl and vams files, and using the -ams is probably not an option.

    Question is: Can anyone suggest a solution? Is there an command line option that I missed, which applies to a single file only?

    Thaks,

    Steven

     

    • Post Points: 20
  • Thu, Oct 18 2012 8:08 AM

    • tpylant
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    RE: irun: design.v is verilog and verilog AMS Reply
    A few thoughts:

    1. Rename the file with a “.vams” extension. Since Verilog-2001 is a subset  of Verilog-AMS, the syntax should compile correctly whether you have the WREAL defined or not.
    2. If for some reason you can’t rename the file or you use SV in the non-wreal code, then you could use a unique filename extension (eg. .sv-vams) and then use “=amsvlog_ext +,.sv-vams” for when you define WREAL or “-sysv_ext +,.sv-vams” for when you don’t define WREAL.
    3. If neither of those work, you could just compile the one file by itself and use the “-ams” switch when you define WREAL and then compile the remaining files using your standard irun command.

    Tim
    • Post Points: 20
  • Thu, Oct 18 2012 8:29 AM

    • moogyd
    • Top 500 Contributor
    • Joined on Mon, Mar 22 2010
    • Posts 23
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    Re: RE: irun: design.v is verilog and verilog AMS Reply

    Hi Tim,

    Thanks for the ideas

    1) This would solve the immediate issue. We are currently not using SV, but will be in future. However, I guess that we would not be mixing wreal and sv in the same file.

    2) Extra marks for "thinking outside the box", but no thanks :-) I don't think this solution would make me very popular within the company.

    3) I had thought of this, but we would then start losing irun advantages.

    One more thought I had is to use a verilog pre-processor+Makefile to auto-generate design.vams from design.v

    For now, I'll go with (1)

    Thanks again for the feedback.

    Steven

    • Post Points: 5
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Started by moogyd at 18 Oct 2012 07:28 AM. Topic has 2 replies.