I am trying to simulate a mixed signal design. The digital part is a hierarchical VHDL design. The digital desing is simulating fine with incisive.
But when I tried ams from whitin virtuoso I received all kinds of errors. I tried a flat design and it works fine. But the errors are for the heirarchical one. An example of instatnce definition I use is below:
coarse_cntr: entity work.reg
WIDTH => COARSE_REG_WIDTH
arst => arst_i,
clk => clk_coarse_q,
en => en_coarse_cntr,
srst => '0',
load => '0',
incr => '1',
shift => '0',
sdi => '0',
di => (others => '0'),
sdo_q => open,
do_q => coarse_cnt_q_i
I added hdl.var file and added the work library in cds.lib as explained in the help, but I still get work library error:
WRKBAD: logical library name WORK is bound to a bad library name WORK
When I remove hdl.var file, I still get a lot of errors due to the statement "entity work.name"
I also noted that the hierarchy is sometimes capture by HED and sometimes not. How can I force compilation of the top module for heirarchy to appear in HED?
Please help if u've done hierarchical VHDL simulation before using AMS