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 Generation of EVCD file for Verilog-AMS 

Last post Tue, Sep 25 2012 1:56 AM by Anky. 0 replies.
Started by Anky 25 Sep 2012 01:56 AM. Topic has 0 replies and 1151 views
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  • Tue, Sep 25 2012 1:56 AM

    • Anky
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    • Joined on Mon, Apr 2 2012
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    Generation of EVCD file for Verilog-AMS Reply

    Hi,

     

    Testbench developed in verilog-AMS and uses wreal as a ports and internal signals.

    When It's tried to generate EVCD for design ports with $dumpports() gives error related to "Wreal is not supported".

    I am using IUS 10.2 version. I need EVCD for vector generation for tester.

     

    Please help me out.

    Thanks in advance.

    Regards,

    Ankit 

    • Post Points: 5
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Started by Anky at 25 Sep 2012 01:56 AM. Topic has 0 replies.