I'm using CADENCE Virtuoso ADE 6.1.3 for mixed simulation. I have to simulate schematic block which is driven by digital pins (clk, rst, ...). I set up a config view using AMS simulator and when I run a simulation I got the following error message in my irun.log :
Elaborating the design hierarchy:
ncelab: *N,SFEDPL: Deploying new SFE in analog engine.
Caching library 'worklib' ....... Done
Core_Can4b I0 ( .Test(Test), .Rst(Rst), .Clk(Clk), .Ipol_rampe(net24),
ncelab: *E,CUVMUR (./netlist.vams,28|13): instance 'simuCore_Can4b.I0' of design unit 'Core_Can4b' is unresolved in 'worklib.simuCore_Can4b:vams'.
ncelab: Memory Usage - 22.1M program + 598.9M data = 621.0M total
ncelab: CPU Usage - 0.0s system + 0.1s user = 0.1s total (0.2s, 59.8% cpu)
irun: *E,ELBERR: Error during elaboration (status 1), exiting.
TOOL: irun 08.20-s029: Exiting on Sep 11, 2012 at 16:58:26 CEST (total: 00:00:01)
Can you help me please ?