what you are trying to do is very complex i think using skill - especially if you have a lot of components. Did you think abouthow you are going to manage flatten pcells? with your approach, it will be very tough using skill.
anyway, one idea could be:
If you have a layout, and if you use a verification tool, why don't you create a netlist from the layout directly (possible with Calibre, i don't know with Assura)
Once you have the spice netlist with all the parameters and the connections, just do a cdl in or a spice in in virtuoso.
Then you have a schematic =)