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 REG:SAME NET VIA PARTIAL CONNECT 

Last post Sat, Mar 2 2013 9:12 PM by Robert Finley. 4 replies.
Started by girish 31 Aug 2012 03:08 AM. Topic has 4 replies and 1212 views
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  • Fri, Aug 31 2012 3:08 AM

    • girish
    • Top 25 Contributor
    • Joined on Wed, Jul 16 2008
    • Bangalore, Karnataka
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    REG:SAME NET VIA PARTIAL CONNECT Reply
    Good Day to All

    How to avoid below circumstance  while doing copper pouring ? .Via’s  not connecting fully /Not fully voiding ?

    One option is to enable same net DRC & manually void in the error area ,its tedious when similar via counts are more .

    Is there any property I can attach to the shape , via ,net , So that like this connections are avoided .
     
    Please suggest
    Thanks
    Regards,
    Girish Kumar
    • Post Points: 50
  • Mon, Sep 10 2012 2:00 AM

    • kabalee
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    Re: REG:SAME NET VIA PARTIAL CONNECT Reply

     you can edit the shape right 

    kabee
    • Post Points: 20
  • Mon, Sep 17 2012 1:04 AM

    • girish
    • Top 25 Contributor
    • Joined on Wed, Jul 16 2008
    • Bangalore, Karnataka
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    Re: REG:SAME NET VIA PARTIAL CONNECT Reply

          Thats True. TIme being did same thing. But I have 1000+ connection like this in 4 to 5 signals layers. Manually editing is difiicult &  time consuming. Want to check Is there any constraint I can set , So that it should void automatically (while doing copper pouring through out the board) if shape is not connecting to the centre of the via.

     Few fabricator reporting  this as a issue if shape not connecting to the centre of the via .

     

    Regards ,

    Girish Kumar 

    • Post Points: 5
  • Sat, Mar 2 2013 5:09 PM

    • Theodor
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    • Milpitas, CA
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    Re: REG:SAME NET VIA PARTIAL CONNECT Reply
    This is a very simple problem to solve.

    Here is how: Looking at the picture, you have the design rules set to something like:  

    • line to line spacing 7 mils
    • line to via 5 mils
    • via to shape 5 mils
    • line to shape 25 mils

    So you allow as little as 5 mils from a via to a shape, but from a line to a shape you ask for 25 mils -- why do you need such a high clearance? Is it for PCB manufacturability or signal integrity (SI)?   PCB manufacturability is definitely not an issue because if you can etch 5 mils between other copper objects, you can do that also around shapes. From SI point of view, if there is GND plane adjacent to this signal plane, that plane is most likely just a few mils away so having the GND shape close is not an issue either.    How to fix the problem: Set the line-shape DRC to the same value as via-shape and you will not have this issue anymore.

    For example, set both to 5 mils or both to 10 mils, or whatever value you are OK with. I see this issue of GND pouring all the time.  I work with a lot of layout designers and I do see the DRC rules are many times quite arbitrarily selected too large.   My recommendation, in general, is to have for all the same-plane, copper-to-copper objects spacings as similar as possible, in any pair combinations of line, via, pad, pin_TH and shape; there are 15 combinations.   

    How to set them the right way?

    1. First, make all of them as small as possible, as allowed by PCB manufacturing and assembly, but do challenge them is they look unreasonably large.  The smaller you can get them the easier will be to complete the board (quite obvious but overlooked).
    2. Then take the largest number off all, and use that for all the other ones.  This way GND pours will work the best and will have the same gap from all the other objects.   Essentially, a GND poor is just another wire that is wider - so treat it as a wire and have for it the same DRC rules as for a wire.

    Hope this answer helps somebody else also as it comes late.   

    Please post some comments if you find anything not right.

    Thanks for reading (and hope useful.)
    • Post Points: 5
  • Sat, Mar 2 2013 9:12 PM

    Re: REG:SAME NET VIA PARTIAL CONNECT Reply

     Usually, in microwave designs, that situation with the vias sticking out tells me that I need to slide thos vias back under the fill boundaries.

     I'm not sure why your clearance between the pour and other nets is so wide.  Parasitic capacitance?

     In the end, many fabricators solve acid-traps with an automatic fillet in CAM.   I don't believe fixing that is necessary.

     

    • Post Points: 5
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Started by girish at 31 Aug 2012 03:08 AM. Topic has 4 replies.