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 ncverilog simulation verilog: error fmuk 

Last post Mon, Aug 27 2012 9:31 AM by weebey. 5 replies.
Started by weebey 24 Aug 2012 07:31 PM. Topic has 5 replies and 3298 views
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  • Fri, Aug 24 2012 7:31 PM

    • weebey
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    ncverilog simulation verilog: error fmuk Reply

    Hi,

    I am trying to run a simulation on my schematic using NC-Verilog in Virtuoso. When I click simuate, I keep getting these errors:

    irun: *E,FMUK: The type of the file (/counter_run1/testfixture.template) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds0/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds1/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds2/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds3/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds4/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds5/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds6/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds7/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds8/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds9/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds10/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds11/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds12/netlist) could not be determined.

    irun: *E,FMUK: The type of the file (ihnl/cds13/netlist) could not be determined.

     

    Does anyone know how to fix this? Thanks. 

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    • Post Points: 20
  • Sun, Aug 26 2012 1:28 PM

    • tpylant
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    Re: ncverilog simulation verilog: error fmuk Reply
    Add '-sv' to your command line options.

    Tim
    • Post Points: 20
  • Mon, Aug 27 2012 7:29 AM

    • weebey
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    Re: ncverilog simulation verilog: error fmuk Reply

    Thanks for the reply, Tim. I actually ended up fixing this problem with the command -default_ext verilog. However, now I am getting error messages like this one:

     nfetx  M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),

            |

    ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.

    ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.

    nfetx  M2 ( .S(cds_globals.gnd_), .G(B), .D(hnet14),

            |

    ncelab: *E,CUVMUR (./ihnl/cds0/netlist,20|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M2' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.

     Do you know what's going on here? I synthesized the design with Design Compiler and then imported it into Virtuoso as a schematic. 

    • Post Points: 20
  • Mon, Aug 27 2012 8:06 AM

    • tpylant
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    Re: ncverilog simulation verilog: error fmuk Reply
    Looks like you need to refer to a cell library that needs to be included on the command line.

    Tim
    • Post Points: 35
  • Mon, Aug 27 2012 8:10 AM

    • weebey
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    Re: ncverilog simulation verilog: error fmuk Reply
    Can I also do this through the gui in Virtuoso? If not, could you explain what I need to do, assuming I know where the library is?
    • Post Points: 5
  • Mon, Aug 27 2012 9:31 AM

    • weebey
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    Re: ncverilog simulation verilog: error fmuk Reply

    I was able to do the following without any errors:

    ncxlmode counter_synth.v -v ibm18.v 

    where counter_synth.v is the netlist to be simulated and ibm18.v is the verilog file for my standard cells. However, I can not figure out how to do this with NC-Verilog within the virtuoso GUI still.

     

    • Post Points: 5
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Started by weebey at 24 Aug 2012 07:31 PM. Topic has 5 replies.