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 LEC and Designware components 

Last post Fri, Aug 17 2012 12:22 PM by affaqq. 1 replies.
Started by jlang 17 Aug 2012 12:21 PM. Topic has 1 replies and 1145 views
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  • Fri, Aug 17 2012 12:21 PM

    • jlang
    • Not Ranked
    • Joined on Tue, Mar 17 2009
    • Dallas, TX
    • Posts 2
    • Points 40
    LEC and Designware components Reply

    Any method to resolve a blackboxed designware component on RTL netlist which does not match up to GATE level netlist? 

    Due to scan insertion on the DW_ram* module in gate leve netlist, LEC will not allow me to match up blackboxes between the golden and revised netlists.

    Any help on this one?  I can see if I have a sythesizable model in RTL this would likely work, but even the DW_ram* provided by LEC is not sythesizable.

     

    • Post Points: 20
  • Fri, Aug 17 2012 12:22 PM

    • affaqq
    • Not Ranked
    • Joined on Mon, Apr 2 2012
    • Torino, Turin
    • Posts 13
    • Points 110
    Re: LEC and Designware components Reply
    I am on vacations so might not be able to respond timely. I will get back to work from 2nd Sept, 2012.


    Ciao!

    Affaq Qamar
    Mob:+3280294862
    • Post Points: 5
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Started by jlang at 17 Aug 2012 12:21 PM. Topic has 1 replies.