Any method to resolve a blackboxed designware component on RTL netlist which does not match up to GATE level netlist?
Due to scan insertion on the DW_ram* module in gate leve netlist, LEC will not allow me to match up blackboxes between the golden and revised netlists.
Any help on this one? I can see if I have a sythesizable model in RTL this would likely work, but even the DW_ram* provided by LEC is not sythesizable.