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 how to add synthesizable delay in design 

Last post Sat, Jul 20 2013 11:26 AM by Paul Bibin. 1 replies.
Started by yasir khan 14 Aug 2012 03:19 PM. Topic has 1 replies and 4991 views
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  • Tue, Aug 14 2012 3:19 PM

    • yasir khan
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    • Joined on Tue, May 3 2011
    • Posts 5
    • Points 55
    how to add synthesizable delay in design Reply

    I am trying to add a delay of 3ns and 5 ns in my design but it not synthesizable in RC-compilor..

    anyone have idea how to add a synthesizable deslay in verilog.....

                                                                                                       thanks 

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    • Post Points: 20
  • Sat, Jul 20 2013 11:26 AM

    • Paul Bibin
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    • Joined on Sat, Jul 20 2013
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    • Points 10
    Re: how to add synthesizable delay in design Reply

    At RTL stage you can add delays either by registers /counter

    However during backend phase delays can be incorporated by adding buffers /delay elements in the design.

    • Post Points: 5
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Started by yasir khan at 14 Aug 2012 03:19 PM. Topic has 1 replies.