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 subc as a symbol vs. extracted view for post layout simulation 

Last post Thu, Aug 2 2012 6:17 PM by tkhan. 1 replies.
Started by bnugent 01 Aug 2012 09:16 AM. Topic has 1 replies.
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  • Wed, Aug 1 2012 9:16 AM

    • bnugent
    • Top 500 Contributor
    • Joined on Thu, Jun 9 2011
    • Cambridge, MA
    • Posts 20
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    subc as a symbol vs. extracted view for post layout simulation Reply

     

    Hi all,

     

    I am using Virtuoso 6.1.4. I have two scenarios that are giving me conflicting results when I run av_analog_extracted simulations. By the way I'm using config to modify which view names the instances use.

     Scenario 1: entire cell is simulated with its view name set to av_analog_extracted

     Results from Scenario 1: The currents in the subcells are the proper magnitudes but the currents are not properly reflected in the metal traces leaving the subcells.

     Scenario 2:  same as Scenario 1, but the subc view name is set to symbol

     Results from Scenario 2: The current in the metal traces appropriately represent the currents from the subcells, however, the magnitudes of the currents are significantly lower than tested. 

     

    Has anyone really dug in to simulations using the config view and observed any of these scenarios having to do with subc?

     

    Thanks in advance,

     

    bnugent 

     

    • Post Points: 20
  • Thu, Aug 2 2012 6:17 PM

    • tkhan
    • Top 50 Contributor
    • Joined on Sat, Aug 16 2008
    • Toronto, Ontario
    • Posts 159
    • Points 2,205
    Re: subc as a symbol vs. extracted view for post layout simulation Reply

    Sounds like you're using an IBM design kit, if so it's probably best to contact them.

    Tarek

    • Post Points: 5
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Started by bnugent at 01 Aug 2012 09:16 AM. Topic has 1 replies.