In my design I have 2 instances of PLL. The PLL A and PLL B are identical with two output pins (synchronous outputs). I have cascaded one of the output port of PLL A to PLL B. My module top/s_inst uses two clocks one from the output of PLL A directly and another from the output of PLL B ( whose input is the cascaded to PLL A). In this case, how should I constrain my clock?
Is it OK if I define the first clock to s_inst from the output pin of PLL A and the second clock to s_inst from the output pin of PLL B.
1) Will the edges of PLL A clock and PLL B clock to s_inst be synchronozed automatically?
2) Should I consider the delay incurred by PLL B as an insertion delay or just don't care about it?
please do help on this.