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 Synthsis of VHDL-2008 on RC 

Last post Thu, Jul 26 2012 7:36 AM by grasshopper. 1 replies.
Started by shahein 26 Jul 2012 03:12 AM. Topic has 1 replies and 1905 views
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  • Thu, Jul 26 2012 3:12 AM

    • shahein
    • Not Ranked
    • Joined on Mon, Feb 23 2009
    • Posts 4
    • Points 35
    Synthsis of VHDL-2008 on RC Reply

    Dear All,

     I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly. 

    However, I am not able to synthesis the same code using RC.

    I am using Cadence 5 flow with RC v10.1.

    What is your recommendations to overcome this issue.

    In waiting for your constructive feedbacks.

    Regards.

    • Post Points: 20
  • Thu, Jul 26 2012 7:36 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Fri, Jul 18 2008
    • Chelmsford, MA
    • Posts 242
    • Points 3,205
    Re: Synthsis of VHDL-2008 on RC Reply

    Hi shahein,

    I suggest you contact your local AE and identify the VHDL-2008 constructs you are seeking support for. VHDL-2008 is not fully supported yet. In fact, I would caution you most EDA tools out there do not FULLY support VHDL-2008

     gh-

     

    • Post Points: 5
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Started by shahein at 26 Jul 2012 03:12 AM. Topic has 1 replies.