For P&R digital parts of my design based on IBM CMOS 7RF, I am making layouts for some gates and trying to export LEF file as standard cells. I have two questions as follows.
1. Since I'm new to P&R, the information about LEF I read is that it contains two parts. Tech part includes process info and design rules, and MACRO part has your layout design info. Then how to generate both of them? For MACRO part I learned that I can generating GDS2 by exporting stream and then import to AG for creating LEF, is that correct flow? And how to generate tech part? Any advices and references would be helpful.
2. When I try to start AG in IC614 by selecting tech lib of IBM7RF, the following errors occur in the log.
ERROR (ABS-216): There are insufficient metal layers defined in the current design. You must define at least two metal layers in the validLayers subsection of LEFDefaultRouteSpec constraint group of the technology file. These layers must have the layer function "metal" in the functions section. Update the technology file and attach it again.
ERROR (ABS-218): There are no vias specified in the technology file. Ensure that the selected constraint group has a ValidVias section or at least one via is specified in the standardViaDefs subsection of the viaDefs section in the technology file. In addition, ensure that the function argument is set to 'cut' for the via in the functions subsection of the layerRules section and then try again.
INFO (ABS-232): Layer summary: 0 metal layer(s), 0 via layer(s), 1 poly layer(s), and 1 diff layer(s) found
INFO (ABS-234): Via summary: 0 valid via(s) found
How come the layers' info is not defined while I can draw the layout? Am I missing anything?
Thanks in advance for your time and helps.