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 Cannot pass parameters from virtuoso sch. into Verilog module 

Last post Tue, Oct 23 2012 9:48 AM by Pavel47. 13 replies.
Started by Pavel47 22 Jul 2012 10:22 AM. Topic has 13 replies and 4212 views
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  • Sun, Jul 22 2012 10:22 AM

    • Pavel47
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    Cannot pass parameters from virtuoso sch. into Verilog module Reply

     Hello,

     I've met problem while passing parameter value, specified on the schematic.

    Here is Verilog module:

    module Pixel_v0 (input Din, CLK, output Dout );
       parameter SEED = 33;
       integer INTSEED=SEED;
       reg [15:0] DATA;
       assign Dout = DATA[15];

    //   initial DATA = $random(INTSEED);
       initial DATA = INTSEED;
      

       generate
          genvar  i;
          for (i = 0; i < 15; i=i+1) begin: DFF
         if (i==0)
           always @(posedge CLK)
             DATA[i] <= Din;
         always @(posedge CLK)
           DATA[i+1] <= DATA[i];
          end
       endgenerate

    endmodule

    On the picture on attachment I shoved concrned instance (with parameter value = 15) and signal waveform. As you can constate, the initial DATA value is 33 (as spicified inside of verilog module), but not 15 (as sppecified in schematic).

    Where is a problem.

    Thanks in advance.

    Pavel. 


    • Post Points: 20
  • Sun, Jul 22 2012 10:33 AM

    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply
    Few things that this could be. First of all, are you netlisting/simulating in ADE with "ams" as the simulator or using the Verilog Integration in the schematic (Launch->Simulation->NC Verilog)?

    And which version of the IC tools are you using (Help->About in CIW will give the subversion)?

    Andrew
    • Post Points: 20
  • Mon, Jul 23 2012 12:55 AM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Hello Andrew,

    I used Launch->Simulation->NC Verilog

    CIW version is IC6.1.5.72

    Thanks.

    Pavel.

    • Post Points: 20
  • Mon, Jul 23 2012 1:02 AM

    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Pavel,

    Since the Verilog netlister is not CDF based, you probably need to set hnlVerilogCDFdefparamList - search in the documention or on Cadence Online Support for more details.

    Andrew.

    • Post Points: 20
  • Mon, Jul 23 2012 3:40 AM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

     Thanks for answer Andrew,

    I googled for a solution and found a hint on the Designer's Guide Forum. Here is it:

     You can either do it through the library manger or through SKILL.

    Lib. Mgr.:
    - Right Mouse click over the desired view
    - Properties
    - [Edit -> Create...]
    - View Property Editor
    - Add
    - hnlVerilogCDFdefparamList <dataType> <value>

    SKILL:

    d_cvId = dbOpenCellViewByType( t_libName t_cellName t_viewName nil "a" )
    dbCreateProp( d_cvId "hnlVerilogCDFdefparamList" "<dataType>"  <value> )
    dbSave( d_cvId )
    dbClose( d_cvId )

    Bern

    Concerned cell has 2 views - symbol and verilog. Where should I add hnlVerilogCDFdefparamList propery ?

    In the initiall message the guy mentionned that  hnlVerilogCDFdefparamList must be added on the switched master of the instance cell. Unfortunately I ignore what doest switched master mean. The post dates 2007, so it's improbable, that I will be answered.

    Regards.

    Pavel.

    • Post Points: 20
  • Mon, Jul 23 2012 3:58 AM

    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Pavel,

    Well, the first suggestion is completely wrong, and the second is unnecessarily complicated.

    It's documented - so searching in cdnshelp is better than Google (I'd always start with a more specific search than assuming Google will find it, given that Google can't see our support portal or see our documentation). It's covered in a Cadence Online Support solution too.

    Regards,

    Andrew.

    • Post Points: 20
  • Mon, Jul 23 2012 10:53 AM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Andrew,

    I've found this info inside of Virtuoso NC Verilog Environment User Guide:

    CDF properties can be used by either creating a Verilog hierprop property or by using hnlVerilogCDFdefparamList parameter.
    If an instance has CDF parameters, the user does not need to create a Verilog hierprop property to ask the Verilog netlister to print out CDF properties by defparam statement. But the user does need to create a hnlVerilogCDFdefparamList property on the switched master of the instance cell.
    property name: hnlVerilogCDFdefparamList
    property type: list type
    property value(example): (“Asim” “Lsim” “l” “w” “Wsim”)
    The Verilog formatter looks first at the instance Verilog hierprop properties and prints out those properties. Then, the formatter looks at the switched master of instance to determine whether property hnlVerilogCDFdefparamList exist.

    But I didn't find what is switched master ?

    I've searched everywhere - cdnshelp, google, etc. - no definition at all.

    Regards.

    Pavel.

    • Post Points: 20
  • Mon, Jul 23 2012 11:19 AM

    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply
    Pavel,

    The switched master is the view that has been switched into by virtue of the switch view list. For a textual verilog view (eg a "functional" view), that would be the functional view itself. Editing the cellView properties on that is a bit tricky, so the best place to put this is in the CDF for the cell.

    That's what the solution I referenced tells you to do.

    None of this is ideal, and there's an enhancement request to be able to pass parameters without needing this magic property, but it's not been implemented yet.

    Best Regards,

    Andrew
    • Post Points: 20
  • Mon, Jul 23 2012 1:54 PM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Andrew,

    I'm afraid I didn't clearly understood your suggestion to add hnlVerilogCDFdefparamList property to cell CDF.

    When I open cell CDF (CIW->Tools->CDF->Edit), I couldn't find list property (as specified in manual) while trying to add new property to the table on the Component Parameter tab.

    So, I renounced CDF and procedeed via Library Manager. There are 2 views for the concerned cell - "symbol" and "verilog". I tried to add hnlVerilogCDFdefparamList property for symbol view: right-click on symbol view -> Properties -> Add (Name: hnlVerilogCDFdefparamList, type: ILList, value: "SEED")-> Apply (please, see the picture in attachment).

    Then I tried to resimulate my testbench. Nothing changed.

    Presumably I was mistaken while trying to interpret explanation.

    Best Regards.
    Pavel.


    • Post Points: 20
  • Mon, Jul 23 2012 2:40 PM

    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Pavel,

    I already told you that the library manager approach was incorrect, so it's not surprising that this wouldn't work.

    The CDF approach is described in th esolution I pointed you to. The key bit is here:

    Approach 1:
    ===========

    Add a CDF parameter named hnlVerilogCDFdefparamList on base CDF of hnmosb cell by going to Tools->CDF->Edit menu

    paramType:   string
    parseAsCEL: yes
    name:  hnlVerilogCDFdefparamList
    prompt: hnlVerilogCDFdefparamList
    defValue:  l w   => You just need to specify name of parameters separated by space.
    display:   nil   => Set it to t if you want to see the values on edit properties form.


    Sure, the documentation should be clearer, but that's why we have a solution to improve upon the documentation until that gets fixed.

    Andrew 

    • Post Points: 35
  • Mon, Jul 23 2012 3:59 PM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

     Yesss ! Works ! Thanks Andrew.

    • Post Points: 5
  • Mon, Aug 20 2012 12:49 PM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

     Andrew,

    Unfortunately the changes aren't kept. So, each time after launching Cadence I have to repeate the procedure.

    Is there some workaround ?

    Thanks.

    Pavel.

    • Post Points: 20
  • Mon, Sep 3 2012 6:36 AM

    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

     Pavel,

    Did you remember to change the CDF type to "Base" (rather than "Effective")? Otherwise it will be done in memory only.

    Andrew.

    • Post Points: 20
  • Tue, Oct 23 2012 9:48 AM

    • Pavel47
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    Re: Cannot pass parameters from virtuoso sch. into Verilog module Reply

    Andrew,

    I didn't touch my Cadence project since some weeks due to other more urgent job. Surprisingly when I came back today, I discovered that concerned feature doesn't work ! As one can constate from attached image, the value specified in schematic isn't taken in account, but default (specified in verilog module) instead. Where is a problem ? From accompagnied windowsit seems thatsettings are correct.

    Thanks in advance.

    Pavel.


    • Post Points: 5
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Started by Pavel47 at 22 Jul 2012 10:22 AM. Topic has 13 replies.