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 to overcome timing slack UNCUSTRAINED for combinational circuit in synthesis report 

Last post Fri, Jul 20 2012 10:38 AM by grasshopper. 1 replies.
Started by pavanomkar 20 Jul 2012 09:49 AM. Topic has 1 replies and 1315 views
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  • Fri, Jul 20 2012 9:49 AM

    • pavanomkar
    • Not Ranked
    • Joined on Fri, Jul 20 2012
    • Hyderabad, Andhra Pradesh
    • Posts 1
    • Points 20
    to overcome timing slack UNCUSTRAINED for combinational circuit in synthesis report Reply

    hi,

    i am designing combinational cicuit design, wrote sdc file using virtual clock and it is showing timing slack unconstrained,can any one help me in this regard 

    • Post Points: 20
  • Fri, Jul 20 2012 10:38 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Fri, Jul 18 2008
    • Chelmsford, MA
    • Posts 242
    • Points 3,205
    Re: to overcome timing slack UNCUSTRAINED for combinational circuit in synthesis report Reply

    Hi Andhra,

     please share your constraints. I suspect you are only clocking the inputs or the outputs when both need a clock reference

     

    gh-

    • Post Points: 5
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Started by pavanomkar at 20 Jul 2012 09:49 AM. Topic has 1 replies.