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 The setup violation for the inclkSrc2reg paths in the layout designed by encounter 

Last post Mon, Jul 16 2012 11:44 AM by zhengyudennis. 14 replies.
Started by zhengyudennis 13 Jul 2012 09:48 AM. Topic has 14 replies and 2903 views
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  • Fri, Jul 13 2012 9:48 AM

    The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply
    Hi everyone,
      I am a learner of encounter (cadence) and meet the setup violation on the inclkSrc2reg group, which is shown as follows:


    Path 1: VIOLATED Setup Check with Pin \DFF_1048/Q_reg /CLK 
    Endpoint:   \DFF_1048/Q_reg /D (^) checked with  leading edge of 'CK'
    Beginpoint: g35                (v) triggered by  leading edge of 'CK'
    Path Groups:  {inclkSrc2reg}
    Other End Arrival Time          0.582
    - Setup                         0.190
    + Phase Shift                   5.000
    - Uncertainty                   0.100
    = Required Time                 5.292
    - Arrival Time                 13.369
    = Slack Time                   -8.077
         Clock Rise Edge                      0.000
         + Input Delay                        0.200
         + Drive Adjustment                   0.717
         = Beginpoint Arrival Time            0.917
         Timing Path:
         +------------------------------------------------------------------------------+ 
         |    Instance     |    Arc     |   Cell   |  Slew | Delay | Arrival | Required | 
         |                 |            |          |       |       |  Time   |   Time   | 
         |-----------------+------------+----------+-------+-------+---------+----------| 
         |                 | g35 v      |          | 1.101 |       |   0.917 |   -7.160 | 
         | U9357           | A v -> Y ^ | INVX1    | 3.186 | 5.666 |   6.583 |   -1.494 | 
         | U9293           | A ^ -> Y v | INVX1    | 1.807 | 1.734 |   8.317 |    0.240 | 
         | U8504           | A v -> Y ^ | INVX1    | 3.386 | 2.575 |  10.892 |    2.814 | 
         | U8477           | A ^ -> Y v | INVX1    | 1.729 | 1.346 |  12.237 |    4.160 | 
         | U6039           | A v -> Y ^ | OAI21X1  | 0.709 | 0.726 |  12.964 |    4.886 | 
         | \DFF_1048/U4    | B ^ -> Y v | MUX2X1   | 0.710 | 0.171 |  13.135 |    5.057 | 
         | \DFF_1048/U3    | A v -> Y ^ | INVX1    | 0.183 | 0.235 |  13.369 |    5.292 | 
         | \DFF_1048/Q_reg | D ^        | DFFPOSX1 | 0.183 | 0.000 |  13.369 |    5.292 | 
         +------------------------------------------------------------------------------+ 
         Clock Rise Edge                      0.000
         + Drive Adjustment                   0.003
         = Beginpoint Arrival Time            0.003
         Other End Path:
         +------------------------------------------------------------------------------+ 
         |    Instance     |    Arc     |   Cell   |  Slew | Delay | Arrival | Required | 
         |                 |            |          |       |       |  Time   |   Time   | 
         |-----------------+------------+----------+-------+-------+---------+----------| 
         |                 | CK ^       |          | 0.021 |       |   0.003 |    8.081 | 
         | CK__L1_I0       | A ^ -> Y ^ | CLKBUF2  | 0.043 | 0.086 |   0.089 |    8.167 | 
         | CK__L2_I1       | A ^ -> Y ^ | CLKBUF3  | 0.058 | 0.124 |   0.213 |    8.290 | 
         | CK__L3_I6       | A ^ -> Y ^ | CLKBUF2  | 0.040 | 0.094 |   0.307 |    8.384 | 
         | CK__L4_I16      | A ^ -> Y ^ | CLKBUF3  | 0.039 | 0.116 |   0.424 |    8.501 | 
         | CK__L5_I48      | A ^ -> Y ^ | CLKBUF1  | 0.047 | 0.071 |   0.495 |    8.572 | 
         | CK__L6_I239     | A ^ -> Y ^ | CLKBUF1  | 0.069 | 0.087 |   0.581 |    8.659 | 
         | \DFF_1048/Q_reg | CLK ^      | DFFPOSX1 | 0.069 | 0.001 |   0.582 |    8.660 | 
         +------------------------------------------------------------------------------+ 

    Here, g35 is the input pin. I am a little bit confused that why the delay of U9357 (only a inverter) can be 5.666 ns. Further, all the setup violations happen on the inclkSrc2reg group. Can somebody tell me how to solve such problem? Thanks very much!

    Best,
    Dennis
    • Post Points: 20
  • Fri, Jul 13 2012 11:25 AM

    • Scrivner
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    You may need to look at the fanout of the U9357 output. It may be that there is a large load due to a large fanout that is causing the large delay. Do you have a max_fanout constraint set? If not try adding this constraint to limit the number of gates each output drives. Also make sure you have set the max_transition constraint as well. The input transition on this device looks a little slow as well.

    • Post Points: 20
  • Fri, Jul 13 2012 1:11 PM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply
    Thanks very much for your suggestion. I use the .sdc file from DC for the timing driven layout design in Encounter. The max_fanout constraint is added in the script for DC compilation? In addition, for the max_transition constraint, where can I find its specific value? Thanks very much for your reply.
    • Post Points: 20
  • Fri, Jul 13 2012 1:45 PM

    • Scrivner
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    You should add the max_fanout and max_transition constraint in both the synthesis constrains file and the Encounter constraints file. The best values to use for each constraint depend on the capabilities of the technology and the requirements of the design.

     To determine a good max_transition, you can look in the standard cell library .lib file and look at the transition timing tables for the clock inputs of flops and the inputs of buffers and inverters. Transition values near the middle of these table should give you a good idea of what typical transitions can be expected from the technology.

     For max_fanout, pick a reasonable number that still produces good transition times.

    • Post Points: 20
  • Fri, Jul 13 2012 2:02 PM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply
    Is the encounter constraint file only .sdc file or other files can be used? Thanks!
    • Post Points: 20
  • Fri, Jul 13 2012 3:48 PM

    • Scrivner
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

     The max_fanout and max_transition should be defined in the encounter constraint file which should be a standard .sdc file.

    • Post Points: 20
  • Fri, Jul 13 2012 6:42 PM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply
    After setting the max_fanout and max_transition, I found no influence on the layout design violation.How can I obtain the fanout number as well as capacitance on that rather small path in the encounter? Or should I get it in the PT?
    • Post Points: 20
  • Mon, Jul 16 2012 7:57 AM

    • Scrivner
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

     In Encounter you can use the report_net command to show the number of sinks and capacitance on the net:

     report_net -pin U9357/Y

    • Post Points: 20
  • Mon, Jul 16 2012 8:51 AM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    Thanks. It helps me a lot.

    Does Encounter have any power optimization during or after the layout design? Thanks very much for your help.

    • Post Points: 20
  • Mon, Jul 16 2012 9:00 AM

    • Scrivner
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

     I don't know much about power optimization in Encounter. I suggest reposting your power optimization question in the forum as a new subject to see if someone else can give you some guidance on that.

    • Post Points: 35
  • Mon, Jul 16 2012 9:34 AM

    • seourani
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    Thanks very much for your suggestion.

    I use the .sdc file from DC for the timing driven layout design in Encounter. The max_fanout constraint is added in the script for DC compilation? In addition, for the max_transition constraint, where can I find its specific value?

    Thanks very much for your reply.

    • Post Points: 20
  • Mon, Jul 16 2012 10:55 AM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    The max_fanout constraint is added in the script for DC compilation

    the value of max_transition constraint is specified according to your clock period and technology file.

    I am also a learner, so we can have a discuss about it. 

    • Post Points: 5
  • Mon, Jul 16 2012 11:17 AM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    One more thing to bother you. Sorry about that.

    From the CTS synthesis in the encounter, I found that the library setup time is strongly related to the clock transition time. I get the following result when 'set_clock_transition 0.5' and the clock period is 3.3 ns.

    Path 1: VIOLATED Setup Check with Pin \DFF_993/Q_reg /CLK 

    Endpoint:   \DFF_993/Q_reg /D (^) checked with  leading edge of 'CK'

    Beginpoint: RESET             (^) triggered by  leading edge of 'CK'

    Path Groups:  {inclkSrc2reg}

    Other End Arrival Time          0.995

    - Setup                         6.838

    + Phase Shift                   3.300

    - Uncertainty                   0.100

    = Required Time                -2.643

    - Arrival Time                  2.523

    = Slack Time                   -5.166

         Clock Rise Edge                      0.000

         + Input Delay                        0.200

         + Drive Adjustment                   0.010

         + Network Insertion Delay            1.000

         = Beginpoint Arrival Time            1.211

         Timing Path:

         +-----------------------------------------------------------------------------+ 

         |    Instance    |    Arc     |   Cell   |  Slew | Delay | Arrival | Required | 

         |                |            |          |       |       |  Time   |   Time   | 

         |----------------+------------+----------+-------+-------+---------+----------| 

         |                | RESET ^    |          | 0.005 |       |   1.210 |   -3.955 | 

         | U6196          | A ^ -> Y v | INVX1    | 0.049 | 0.046 |   1.256 |   -3.909 | 

         | U6219          | A v -> Y ^ | INVX1    | 0.086 | 0.081 |   1.338 |   -3.828 | 

         | U6255          | A ^ -> Y v | INVX1    | 0.091 | 0.094 |   1.432 |   -3.734 | 

         | U6254          | A v -> Y v | BUFX2    | 0.075 | 0.098 |   1.530 |   -3.636 | 

         | U3685          | C v -> Y ^ | NOR3X1   | 0.181 | 0.128 |   1.658 |   -3.508 | 

         | U4769          | A ^ -> Y v | INVX1    | 0.050 | 0.097 |   1.755 |   -3.411 | 

         | U6160          | A v -> Y ^ | INVX1    | 0.022 | 0.042 |   1.797 |   -3.369 | 

         | U5856          | A ^ -> Y v | INVX1    | 0.044 | 0.042 |   1.839 |   -3.327 | 

         | U5855          | A v -> Y ^ | INVX1    | 0.159 | 0.119 |   1.958 |   -3.208 | 

         | U5756          | A ^ -> Y v | INVX1    | 0.098 | 0.121 |   2.079 |   -3.087 | 

         | U5533          | A v -> Y ^ | INVX1    | 0.142 | 0.130 |   2.209 |   -2.956 | 

         | U2094          | C ^ -> Y v | AOI22X1  | 0.143 | 0.050 |   2.260 |   -2.906 | 

         | U4256          | B v -> Y v | AND2X2   | 0.037 | 0.073 |   2.333 |   -2.833 | 

         | U4257          | A v -> Y ^ | INVX1    | 0.478 | 0.017 |   2.350 |   -2.815 | 

         | \DFF_993/U4    | B ^ -> Y v | MUX2X1   | 0.091 | 0.135 |   2.486 |   -2.680 | 

         | \DFF_993/U3    | A v -> Y ^ | INVX1    | 0.000 | 0.037 |   2.523 |   -2.643 | 

         | \DFF_993/Q_reg | D ^        | DFFPOSX1 | 0.000 | 0.000 |   2.523 |   -2.643 | 

         +-----------------------------------------------------------------------------+ 

         Clock Rise Edge                      0.000

         + Drive Adjustment                   0.003

         = Beginpoint Arrival Time            0.003

         Other End Path:

         +-----------------------------------------------------------------------------+ 

         |    Instance    |    Arc     |   Cell   |  Slew | Delay | Arrival | Required | 

         |                |            |          |       |       |  Time   |   Time   | 

         |----------------+------------+----------+-------+-------+---------+----------| 

         |                | CK ^       |          | 0.022 |       |   0.004 |    5.169 | 

         | CK__L1_I0      | A ^ -> Y ^ | CLKBUF2  | 0.014 | 0.069 |   0.073 |    5.239 | 

         | CK__L2_I0      | A ^ -> Y ^ | CLKBUF2  | 0.016 | 0.070 |   0.143 |    5.309 | 

         | CK__L3_I0      | A ^ -> Y ^ | CLKBUF3  | 0.016 | 0.097 |   0.240 |    5.406 | 

         | CK__L4_I0      | A ^ -> Y ^ | CLKBUF3  | 0.030 | 0.106 |   0.346 |    5.511 | 

         | CK__L5_I0      | A ^ -> Y ^ | CLKBUF2  | 0.039 | 0.089 |   0.435 |    5.600 | 

         | CK__L6_I0      | A ^ -> Y ^ | CLKBUF1  | 0.337 | 0.239 |   0.674 |    5.839 | 

         | CK__L7_I9      | A ^ -> Y ^ | CLKBUF2  | 0.397 | 0.312 |   0.986 |    6.152 | 

         | \DFF_993/Q_reg | CLK ^      | DFFPOSX1 | 0.398 | 0.009 |   0.995 |    6.161 | 

         +-----------------------------------------------------------------------------+  

     So, How can I reduce the library setup time in encounter? Thanks very much!

     

    • Post Points: 20
  • Mon, Jul 16 2012 11:32 AM

    • Scrivner
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    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply

    In your CTS config file *.ctstch you will need to reduce your max clock transition.

    • Post Points: 20
  • Mon, Jul 16 2012 11:44 AM

    Re: The setup violation for the inclkSrc2reg paths in the layout designed by encounter Reply
    I found that if I reduce the clock transition time in DC, than the synthesis procedure will be very difficult to finish. It seems that the larger clock transition time, the larger library setup time. Is it right?
    • Post Points: 5
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Started by zhengyudennis at 13 Jul 2012 09:48 AM. Topic has 14 replies.