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 Reflections and impedance mismatch simulations 

Last post Wed, Jan 2 2013 4:50 AM by Andrew Beckett. 1 replies.
Started by sohaibafridi 06 Jul 2012 08:01 AM. Topic has 1 replies and 1328 views
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  • Fri, Jul 6 2012 8:01 AM

    • sohaibafridi
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    • Joined on Sat, Dec 24 2011
    • <?xml version="1.0" encoding="utf-16"?><string>Islamabad, Pakistan</string>
    • Posts 12
    • Points 210
    Reflections and impedance mismatch simulations Reply

     Does Cadence Virtuoso simulates reflections due to impedance mismatch in a simple trans simulations simply because of the RLC present in the circuit and also that I don't use any transmission-line or waveguide models in the path or any other distributed parameter?

    i.e. during transient simulations do we get the effects of the reflected voltages at each interface when the interfaces have slightly different impedances, similar to the impedance mismatch of the transmission lines as we study them in RF?

    Regards

    Sohaib Afridi
    • Post Points: 20
  • Wed, Jan 2 2013 4:50 AM

    Re: Reflections and impedance mismatch simulations Reply

     Yes.

    • Post Points: 5
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Started by sohaibafridi at 06 Jul 2012 08:01 AM. Topic has 1 replies.