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 LVS not running 

Last post Mon, Aug 27 2012 5:26 PM by Quek. 8 replies.
Started by Sarvani 28 Jun 2012 11:54 PM. Topic has 8 replies and 3329 views
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  • Thu, Jun 28 2012 11:54 PM

    • Sarvani
    • Top 75 Contributor
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    • VIZAG, Andhra Pradesh
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    LVS not running Reply

    Hi all,

    1)         I got following error in log file when I run LVS. Is there any need of schematic change or Compare rule file change.

             ** Parallel MOS combined:
      1st MOS: L = 3e-08 W = 4e-07 m = 1
      2nd MOS: L = 3e-08 W = 2e-07 m = 1
      Resulting: L = 3e-08 W = 6e-07 m = 1
    *Error* times: can't handle ("1" * 6e-07)
    *ERROR* User supplied SKILL routine failed: '(compareMOS)'. SKILL interpreter could not execute this SKILL function.
        Probably usage of the function is not correct. Try to revise the syntax:
        (compareMOS('(nil l 3e-08 w 6e-07 m 1) '(nil m "1" l 3e-08 w 6e-07)))


    *****  nvn fork terminated abnormally  *****\

    In compare rule file for comparision of mos devices:

      procedure( compareMOS( layPlist, schPlist )
        prog( (missingLay missingSch)

    ; IF m (m factor) IS MISSING, SET IT TO 1

          when( !layPlist->m  layPlist->m = float(1) )
          when( !schPlist->m  schPlist->m = float(1) )

    ; IF W or L IS MISSING GENERATE A PARAMETER MISMATCH
                
          foreach( prop '( w l )
            unless( get( layPlist prop )
              missingLay = cons( prop missingLay )
            ) ;unless
            unless( get( schPlist prop )
              missingSch = cons( prop missingSch )
            ) ;unless
          ) ;foreach

    ; REPORT ALL MISSING PARAMETERS

          when( ( missingLay || missingSch )
        when( missingSch
           sprintf( msg1 "Sch MOS missing parameters: %s"
                 buildString( missingSch ","))
        ) ;when
        when( !missingSch
           sprintf( msg1 "Sch MOS W/L/m %g %g %g"
         float(schPlist->w) float(schPlist->l) float(schPlist->m) )
        ) ;when
        when( missingLay
           sprintf( msg2 "Lay MOS missing parameters: %s"
             buildString( missingLay ",") )
        ) ;when
        when( !missingLay
           sprintf( msg2 "Lay MOS W/L/m %g %g %g"
         float(layPlist->w) float(layPlist->l) float(layPlist->m) )
        ) ;when
        sprintf( msg "Err: %s ; %s" msg1 msg2 )
        return( msg )
          ) ;when
     
    ;  SETTING VARIABLES

          layM = layPlist->m
          layW = float( layM * layPlist->w )
          layL = float( layPlist->l )
          schM = schPlist->m
          schW = float( schM * schPlist->w )
          schL = float( schPlist->l )
          
          diffW = 100 * (abs( layW - schW ) / schW )
          diffL = 100 * (abs( layL - schL ) / schL )
          Werr  = nil
          Lerr  = nil
          
          when( diffW > mosW_lvsTol Werr = t )
          when( diffL > mosL_lvsTol Lerr = t )

    ; IF NO ERRORS RETURN NIL

          when( !Werr && !Lerr  return(nil) )
             sprintf( msg "Err: MOS Sch L/W %g %g; Lay L/W %g %g"
              schL schW layL layW  )
            return( msg )

       ) ; end prog
      ) ; end compareMOS


    ; ************************************************************************

     

    2) I need virtual connection set up when I run LVS. I mean when we add same labels or pins for two nets in layout then it will automatically take that as same net.

     

    Thank you,

    sarvani.

     

    • Post Points: 20
  • Fri, Jun 29 2012 11:31 PM

    • Quek
    • Top 10 Contributor
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    Re: LVS not running Reply

    Hi Sarvani

    It is quite strange that schematic mfactor has been turned into a string. I think you can resolve the first problem as follows:

    === original ===
    schM = schPlist->m

    === New ===
    schM = schPlist->m
    when( stringp(schM) schM=atof(schM))

    For the 2nd problem, please use enable "Additional functions" on Assura LVS form and use "joinableNets" function. Please refer to Assura command reference for more details.

    Best regards
    Quek

    • Post Points: 20
  • Tue, Jul 10 2012 6:09 AM

    • Sarvani
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    Re: LVS not running Reply

     Hi Quek,

                 I am very greatful to you. I followed your suggitions. Its working good and sorry for delay replay.

    Thank you,

    sarvani.

    • Post Points: 5
  • Thu, Jul 12 2012 4:11 AM

    • Sarvani
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    Re: LVS not running Reply
    Hi Quek,
                   I have written resistor(rphpoly) in LVS Rule files. Then it shows following errors.

    ===============================================================================
    ****** Layout network is empty.  Pins match OK. ******
    ===============================================================================

    And Wornings in .wrn file


    Assura Errors & Warnings Search (PLEASE CAREFULLY REVIEW THESE MESSAGES)
    ================================================================================
    WARNINGS & ERRORS found in Assura NVN Run Log file
    --------------------------------------------------------------------------------
     WARNING (AVLVSNN-10050) : resDevice - cell 'rphpoly' not found.
     WARNING (AVLVSNN-10050) : mosDevice - cell 'spcnmos' not found.
     WARNING (AVLVSNN-10050) : mosDevice - cell 'spcpmos' not found.
    *ERROR* Device 'rphpoly(RES)' on Schematic is unbound to any Layout device.
    *ERROR* Device 'spcnmos(MOS)' on Schematic is unbound to any Layout device.


    I wrote like this Rule files :
    In Compare rule file :

    schematic(
        genericDevice( emptySubckt )

        mosDevice( "spcpmos" ( "D" "G" "S" "B" ) "w" "l" )
        mosDevice( "spcnmos" ( "D" "G" "S" "B" ) "w" "l" )
        resDevice( "rphpoly" ( "PLUS" "MINUS" "SUB") "r"  )

        )

      layout(
        mosDevice( "spcpmos" ( "D" "G" "S" "B" ) "w" "l" )
        mosDevice( "spcnmos" ( "D" "G" "S" "B"  ) "w" "l" )
        resDevice( "rphpoly" ( "PLUS" "MINUS" "SUB") "r" )
        )
      mergeParallel( "spcpmos(MOS)" merge parallelMOS )
      mergeParallel( "spcnmos(MOS)" merge parallelMOS )
      mergeSeries( "spcpmos(MOS)" noMerge )
      mergeSeries( "spcnmos(MOS)" noMerge )
    mergeParallel( "rphpoly(RES)" merge parallelRES )
     mergeSeries( "rphpoly(RES)" merge serialRES )

     compareParameter( "spcpmos(MOS)" compareMOS )
      compareParameter( "spcnmos(MOS)" compareMOS )
     ;compareParameter( "rphpoly(RES)"); percent("r" 2) )


    ) ;end avCompareRules

    In Extract rule file:

    extractDevice("rphpoly"  rphpoly cpoly("PLUS" optional("MINUS")) nwell("SUB")
        bulkLayers(nwell) spiceModel("rphpoly") cellView( "rphpoly ivpcell")
        namePrefix("XR") flagMalformed)

        width  = measureParameter( length (rphpoly  butting cpoly ) 0.5 )
        perim  = measureParameter( length (rphpoly  coincident rpdmy ) 0.5 )
        length = calculateParameter( perim - width )

        res    = calculateParameter( (length * rho) / (width - deltaW) )

        normalizedWidth  = calculateParameter( width * 1u )
        normalizedLength = calculateParameter( length * 1u )

        nameParameter( normalizedLength "l" )
        nameParameter( normalizedWidth "w" )
        nameParameter( res "r" )
        nameParameter( normalizedLength "lSim" ); REQUIRED FOR SPECTRE
        nameParameter( normalizedWidth "wSim" ) ; REQUIRED FOR SPECTRE


    Please give me suggestions to over came this.

    Thank you,
    sarvani


    • Post Points: 20
  • Thu, Jul 12 2012 4:38 AM

    • Quek
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    Re: LVS not running Reply

    Hi Sarvani

    It looks like this is an extraction problem and not a comparison problem. Your layout resistors cannot be extracted. I think you will need to re-check your extraction rule for the resistors.


    Best regards
    Quek

    • Post Points: 5
  • Thu, Jul 12 2012 5:42 AM

    • Sarvani
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    Re: LVS not running Reply
    Yes your guess is right. Now it works. I missed one layer on device. Thank you for sharing your knowledge. Thank you once again.
     
    Thank you,
    venu
    • Post Points: 5
  • Fri, Aug 24 2012 6:35 AM

    • Sarvani
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    Re: LVS not running Reply

     Hi Quek,

                  Is there any set up is required for hirerchy LVS checkup. When I am running LVS for top level cellview then Net and Devices errors are occured. In nets report it is showing that less no. of nets in schematic than layout. For example I have VDD in Schematic and layout then in LVS error report it showing that schematic has 1 net for VDD ( I mean VDD(1)) but 8 nets(mean VDD(8)) in layout. For more information please reder to the LVS error report. Please let me know if any set up is needed. Please ignore parameter errors.

    *******************************************************************************
    ****** Current_S_B schematic Dac_Schematics  <vs>  Current_S_B layout1 gangak_28nm
    *******************************************************************************

    Filter/Reduce statistics only. Network matching was OK.
                                                                                                                                                                      
    Pre-expand Statistics                     
    ======================                          Original      
    Cell/Device                               schematic  layout
    (spcnmos) MOS                                     4       7*
    (spcpmos) MOS                                     2       8*
                                                 ------  ------
    Total                                             6      15

    Reduce Statistics
    =================                               Original             Reduced
    Cell/Device                               schematic  layout   schematic  layout
    (spcnmos) MOS                                     4       7*          2       2
    (spcpmos) MOS                                     2       8*          2       2
    (spcnmos:SerMos2#1) MosBlk                        -       -           1       1
                                                 ------  ------      ------  ------
    Total                                             6      15           5       5

    *******************************************************************************
    ****** Current_Sources schematic Dac_Schematics  <vs>  Current_Sources layout gangak_28nm
    *******************************************************************************

    Filter/Reduce statistics only. Network matching was OK.
                                                                                                                                                                      
    Pre-expand Statistics                     
    ======================                          Original      
    Cell/Device                               schematic  layout
    (spcnmos) MOS                                     8       8
                                                 ------  ------
    Total                                             8       8

    Reduce Statistics
    =================                               Original             Reduced
    Cell/Device                               schematic  layout   schematic  layout
    (spcnmos) MOS                                     8       8           8       8
                                                 ------  ------      ------  ------
    Total                                             8       8           8       8

    *******************************************************************************
    ****** DAC schematic gangak_28nm  <vs>  DAC layout1 gangak_28nm
    *******************************************************************************
                                                                                                                                                                                                                               
    Pre-expand Statistics                     
    ======================                          Original      
    Cell/Device                               schematic  layout
    (rphpoly) RES                                    81      84*
    (spcnmos) MOS                                     1      15*
    (Bias_generator schematic Dac_Sch...) Cell        1       0*
    (Current_S_B schematic Dac_Schema...) Cell        1       1
    (Current_Sources schematic Dac_Sc...) Cell        1       1
    (Inverter schematic Dac_Schematic...) Cell        8       0*
    (Opamp schematic Dac_Schematics, _) Cell          1       0*
    (_, pres10k layout gangak_28nm) Cell              0       8*
    (_, P_T_Switch layout2 gangak_28nm) Cell          0       8*
    (_, pres1 layout gangak_28nm x=3 y=4) Cell        0       6*
    (spcpmos) MOS                                     0      25*
                                                 ------  ------
    Total                                            94     148

    Reduce Statistics
    =================                               Original             Reduced
    Cell/Device                               schematic  layout   schematic  layout
    (Current_S_B) Cell                                1       1           1       1
    (Current_Sources) Cell                            1       1           1       1
    (spcnmos) MOS                                    17     111*         15      30*
    (spcpmos) MOS                                    15     121*         15      31*
    (rphpoly) RES                                    84      84           4      17*
    (spcnmos:SerMos2#1) MosBlk                        -       -           1       1

    Match Statistics
    ================                                  Total             Unmatched
    Cell/Device                               schematic  layout   schematic  layout
    (Current_S_B) Cell                                1       1           0       0
    (Current_Sources) Cell                            1       1           0       0
    (spcnmos) MOS                                    15      30*          1      16*
    (spcpmos) MOS                                    15      31*          0      16*
    (rphpoly) RES                                     4      17*          0      13*
    (spcnmos:SerMos2#1) MosBlk                        1       1           0       0
                                                 ------  ------      ------  ------
    Total                                            37      81           1      45

    Match Statistics for Nets                        38      45           0       7

    ==========================================================================[DAC]
    ====== Bad Initial Net Bindings (nets don't match) ============================
    ===============================================================================

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 1)
    Schematic Net:  B7
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B7
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 2)
    Schematic Net:  B6
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B6
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 3)
    Schematic Net:  B4
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B4
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 4)
    Schematic Net:  B3
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B3
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 5)
    Schematic Net:  B2
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B2
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 6)
    Schematic Net:  B1
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B1
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 7)
    Schematic Net:  B0
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B0
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 8)
    Schematic Net:  B5
    S       1   of spcpmos G
    S       1   of spcnmos G

    Layout Net:  B5
    L      *2   of spcpmos G
    L      *2   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badbind 9)
    Schematic Net:  VINM
    S       1   of spcpmos G
    S      *1   of spcnmos G
    S       2   of rphpoly {PLUS MINUS}

    Layout Net:  VINM
    L      *1   of spcpmos {D S}
    L       1   of spcpmos G
    L      *1   of spcnmos {D S}
    L       2   of rphpoly {PLUS MINUS}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badbind 10)
    Schematic Net:  OUT
    S       1   of spcpmos {D S}
    S       3   of spcnmos {D S}
    S       1   of rphpoly {PLUS MINUS}

    Layout Net:  OUT
    L       1   of spcpmos {D S}
    L      *1   of spcnmos {D S}
    L       1   of rphpoly {PLUS MINUS}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badbind 11)
    Schematic Net:  VDD
    S       13  of spcpmos {D S}
    S       14  of spcpmos B
    S       1   of rphpoly {PLUS MINUS}
    S       4   of rphpoly SUB
    S       1   of Current_S_B VDD

    Layout Net:  VDD
    L       13  of spcpmos {D S}
    L      *30  of spcpmos B
    L      *7   of rphpoly {PLUS MINUS}
    L      *17  of rphpoly SUB
    L       1   of Current_S_B VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badbind 12)
    Schematic Net:  VSS
    S       1   of spcpmos B
    S       12  of spcnmos {D S}
    S       15  of spcnmos B
    S       1   of rphpoly {PLUS MINUS}
    S       1   of Current_Sources VSS
    S       1   of Current_S_B VSS
    S       1   of spcnmos:SerMos2#1 {OUT OUT2}
    S       1   of spcnmos:SerMos2#1 TERM4

    Layout Net:  VSS
    L       1   of spcpmos B
    L       12  of spcnmos {D S}
    L      *30  of spcnmos B
    L       1   of rphpoly {PLUS MINUS}
    L       1   of Current_Sources VSS
    L       1   of Current_S_B VSS
    L       1   of spcnmos:SerMos2#1 {OUT OUT2}
    L       1   of spcnmos:SerMos2#1 TERM4

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badbind 13)
    Schematic Net:  VGND
    S       1   of spcpmos G

    Layout Net:  VGND
    L      *8   of spcpmos {D S}
    L       1   of spcpmos G
    L      *8   of spcnmos {D S}

    ==========================================================================[DAC]
    ====== Unmatched Internal Nets ================================================
    ===============================================================================

    L ?avC26
    L ?avC30
    L ?avC49
    L ?avC71
    L ?avC31
    L ?avC53
    L ?avC75

    ==========================================================================[DAC]
    ====== Bad Matched Nets (don't really match) ==================================
    ===============================================================================

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 1)
    Schematic Net:  S0
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC98
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 2)
    Schematic Net:  S1
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC105
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 3)
    Schematic Net:  S2
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC104
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 4)
    Schematic Net:  S3
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC103
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 5)
    Schematic Net:  S4
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC101
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 6)
    Schematic Net:  S5
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC100
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 7)
    Schematic Net:  S6
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC99
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 8)
    Schematic Net:  S7
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    Layout Net:  avC102
    L      *2   of spcpmos {D S}
    L      *2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badmatch 9)
    Schematic Net:  net0283
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I187/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 10)
    Schematic Net:  net0262
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I183/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 11)
    Schematic Net:  net050
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I179/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 12)
    Schematic Net:  net036
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I178/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 13)
    Schematic Net:  net064
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I181/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 14)
    Schematic Net:  net0277
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I180/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 15)
    Schematic Net:  net0279
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I184/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (badmatch 16)
    Schematic Net:  net0278
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}

    Layout Net:  I185/avC7
    L       1   of spcpmos {D S}
    L      *1   of spcpmos G
    L       1   of spcnmos {D S}
    L      *1   of spcnmos G

    ==========================================================================[DAC]
    ====== Shorted Pins ===========================================================
    ===============================================================================

    Layout pin B0 shorted to
    S        B7
    S        B6

    Layout pin B1 shorted to
    S        B4
    S        B3

    Layout pin B2 shorted to
    S        B2
    S        B1

    Layout pin B3 shorted to
    S        B0
    S        B5

    ==========================================================================[DAC]
    ====== Problem Schematic Nets (no exact match in layout) ======================
    ===============================================================================
    S
    S ?VGND
    S       1   of spcpmos G
    S
    S ?S0 ?S1 ?S2 ?S3 ?S4 ?S5 ?S6 ?S7
    S (total 8) with:
    S       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}
    S
    S ?net0283 ?net0262 ?net050 ?net036 ?net064 ?net0277 ?net0279 ?net0278
    S (total 8) with:
    S       1   of spcpmos {D S}
    S       1   of spcnmos {D S}
    S
    S ?B7 ?B6 ?B4 ?B3 ?B2 ?B1 ?B0 ?B5
    S (total 8) with:
    S       1   of spcpmos G
    S       1   of spcnmos G
    S
    S ?OUT
    S       1   of spcpmos {D S}
    S       3   of spcnmos {D S}
    S       1   of rphpoly {PLUS MINUS}
    S
    S ?VINM
    S       1   of spcpmos G
    S       1   of spcnmos G
    S       2   of rphpoly {PLUS MINUS}
    S
    S ?VDD
    S       13  of spcpmos {D S}
    S       14  of spcpmos B
    S       1   of rphpoly {PLUS MINUS}
    S       4   of rphpoly SUB
    S       1   of Current_S_B VDD
    S
    S ?VSS
    S       1   of spcpmos B
    S       12  of spcnmos {D S}
    S       15  of spcnmos B
    S       1   of rphpoly {PLUS MINUS}
    S       1   of Current_Sources VSS
    S       1   of Current_S_B VSS
    S       1   of spcnmos:SerMos2#1 {OUT OUT2}
    S       1   of spcnmos:SerMos2#1 TERM4

    ==========================================================================[DAC]
    ====== Problem Layout Nets (no exact match in schematic) ======================
    ===============================================================================
    L
    L ?B0 ?B1 ?B2 ?B3 ?B4 ?B5 ?B6 ?B7
    L (total 8) with:
    L       2   of spcpmos G
    L       2   of spcnmos G
    L
    L ?OUT
    L       1   of spcpmos {D S}
    L       1   of spcnmos {D S}
    L       1   of rphpoly {PLUS MINUS}
    L
    L ?avC26
    L       1   of spcpmos {D S}
    L       1   of spcnmos {D S}
    L       2   of rphpoly {PLUS MINUS}
    L
    L ?avC30 ?avC49 ?avC71 ?avC31 ?avC53 ?avC75
    L (total 6) with:
    L       1   of spcpmos {D S}
    L       1   of spcnmos {D S}
    L       3   of rphpoly {PLUS MINUS}
    L
    L ?avC98 ?avC105 ?avC104 ?avC103 ?avC101 ?avC100 ?avC99 ?avC102
    L (total 8) with:
    L       2   of spcpmos {D S}
    L       2   of spcnmos {D S}
    L       1   of Current_Sources {S0 S1 S2 S3 S4 S5 S6 S7}
    L
    L ?VGND
    L       8   of spcpmos {D S}
    L       1   of spcpmos G
    L       8   of spcnmos {D S}
    L
    L ?I178/avC7 ?I179/avC7 ?I181/avC7 ?I180/avC7 ?I187/avC7 ?I185/avC7 ?I184/avC7
    L ?I183/avC7
    L (total 8) with:
    L       1   of spcpmos {D S}
    L       1   of spcpmos G
    L       1   of spcnmos {D S}
    L       1   of spcnmos G
    L
    L ?VINM
    L       1   of spcpmos {D S}
    L       1   of spcpmos G
    L       1   of spcnmos {D S}
    L       2   of rphpoly {PLUS MINUS}
    L
    L ?VDD
    L       13  of spcpmos {D S}
    L       30  of spcpmos B
    L       7   of rphpoly {PLUS MINUS}
    L       17  of rphpoly SUB
    L       1   of Current_S_B VDD
    L
    L ?VSS
    L       1   of spcpmos B
    L       12  of spcnmos {D S}
    L       30  of spcnmos B
    L       1   of rphpoly {PLUS MINUS}
    L       1   of Current_Sources VSS
    L       1   of Current_S_B VSS
    L       1   of spcnmos:SerMos2#1 {OUT OUT2}
    L       1   of spcnmos:SerMos2#1 TERM4

    ==========================================================================[DAC]
    ====== Matched Instances with Bad Net Connections =============================
    ===============================================================================

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 1)
    Schematic Instance: R95  rphpoly
    Layout Instance:    avD12_3  rphpoly

    Pin        SchNet                      : LayNet
    ---        ------                      : ------
    PLUS       VDD                         : VINM
    MINUS      VINM                        : ?avC31

    ==========================================================================[DAC]
    ====== Unmatched Schematic Instances ==========================================
    ===============================================================================

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (schinst 1)
    Schematic Instance: M0  spcnmos

    S Pin        Net
    S ---        ---
    S D          OUT
    S G          VINM
    S S          OUT
    S B          VSS

    ==========================================================================[DAC]
    ====== Unmatched Layout Instances =============================================
    ===============================================================================

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 1)
    Layout Instance:    avD12_4  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       VDD
    L MINUS      ?avC31
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 2)
    Layout Instance:    avD12_6  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC31
    L MINUS      ?avC53
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 3)
    Layout Instance:    avD12_7  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       VDD
    L MINUS      ?avC53
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 4)
    Layout Instance:    avD12_9  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC53
    L MINUS      ?avC75
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 5)
    Layout Instance:    avD12_10  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       VDD
    L MINUS      ?avC75
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 6)
    Layout Instance:    avD12_43  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC30
    L MINUS      ?avC49
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 7)
    Layout Instance:    avD12_46  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC49
    L MINUS      ?avC71
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 8)
    Layout Instance:    avD12_49  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC71
    L MINUS      ?avC75
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (layinst 9)
    Layout Instance:    avD12_72  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       VDD
    L MINUS      ?avC49
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 10)
    Layout Instance:    avD12_75  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       VDD
    L MINUS      ?avC71
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 11)
    Layout Instance:    avD12_80  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC26
    L MINUS      VDD
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 12)
    Layout Instance:    avD12_82  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       ?avC30
    L MINUS      ?avC26
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 13)
    Layout Instance:    avD12_83  rphpoly

    L Pin        Net
    L ---        ---
    L PLUS       VDD
    L MINUS      ?avC30
    L SUB        VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 14)
    Layout Instance:    I178/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B7
    L S          S7
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 15)
    Layout Instance:    I178/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S7
    L G          net036
    L S          ?avC26
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 16)
    Layout Instance:    I178/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC26
    L G          B7
    L S          S7
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 17)
    Layout Instance:    I178/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S7
    L G          net036
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 18)
    Layout Instance:    I179/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B6
    L S          S6
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 19)
    Layout Instance:    I179/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S6
    L G          net050
    L S          ?avC30
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 20)
    Layout Instance:    I179/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC30
    L G          B6
    L S          S6
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 21)
    Layout Instance:    I179/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S6
    L G          net050
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 22)
    Layout Instance:    I181/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B5
    L S          S5
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 23)
    Layout Instance:    I181/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S5
    L G          net064
    L S          ?avC49
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 24)
    Layout Instance:    I181/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC49
    L G          B5
    L S          S5
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 25)
    Layout Instance:    I181/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S5
    L G          net064
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 26)
    Layout Instance:    I180/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B4
    L S          S4
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 27)
    Layout Instance:    I180/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S4
    L G          net0277
    L S          ?avC71
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 28)
    Layout Instance:    I180/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC71
    L G          B4
    L S          S4
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 29)
    Layout Instance:    I180/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S4
    L G          net0277
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 30)
    Layout Instance:    I187/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B0
    L S          S0
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 31)
    Layout Instance:    I187/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S0
    L G          net0283
    L S          VINM
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 32)
    Layout Instance:    I187/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          VINM
    L G          B0
    L S          S0
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 33)
    Layout Instance:    I187/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S0
    L G          net0283
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 34)
    Layout Instance:    I185/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B1
    L S          S1
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 35)
    Layout Instance:    I185/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S1
    L G          net0278
    L S          ?avC31
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 36)
    Layout Instance:    I185/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC31
    L G          B1
    L S          S1
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 37)
    Layout Instance:    I185/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S1
    L G          net0278
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 38)
    Layout Instance:    I184/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B2
    L S          S2
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 39)
    Layout Instance:    I184/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S2
    L G          net0279
    L S          ?avC53
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 40)
    Layout Instance:    I184/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC53
    L G          B2
    L S          S2
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 41)
    Layout Instance:    I184/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S2
    L G          net0279
    L S          VGND
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 42)
    Layout Instance:    I183/avD1_4  spcnmos

    L Pin        Net
    L ---        ---
    L D          VGND
    L G          B3
    L S          S3
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 43)
    Layout Instance:    I183/avD1_10  spcnmos

    L Pin        Net
    L ---        ---
    L D          S3
    L G          net0262
    L S          ?avC75
    L B          VSS

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 44)
    Layout Instance:    I183/avD2_4  spcpmos

    L Pin        Net
    L ---        ---
    L D          ?avC75
    L G          B3
    L S          S3
    L B          VDD

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(layinst 45)
    Layout Instance:    I183/avD2_10  spcpmos

    L Pin        Net
    L ---        ---
    L D          S3
    L G          net0262
    L S          VGND
    L B          VDD

    ==========================================================================[DAC]
    ====== Parameter Mismatches for Instances =====================================
    ===============================================================================

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 1)
    Schematic Instance: R100  rphpoly
    Layout Instance:    avD12_13  rphpoly

    r 1000 vs 7.65321 differs by 99.2347%

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 2)
    Schematic Instance: R95  rphpoly
    Layout Instance:    avD12_3  rphpoly

    r 8000 vs 30.6128 differs by 99.6173%
    Schematic Instance is the merged result of:  R95 R94 R93 R92 R91 R90 R89 R88
            R87 R86 R85 R84 R83 R82 R81 R80 R79 R78 R77 R76 R75 R74 R73 R72 R97 R99
            R98 R59 R58 R57 R56 R96 R47 R46 R45 R44 R43 R42 R41 R40 R39 R38 R37 R36
            R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 R25 R24 R23 R22 R21 R20 R19 R18
            R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
    Layout Instance is the merged result of:  avD12_3 avD12_14 avD12_23 avD12_32

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 3)
    Schematic Instance: X0/R1  rphpoly
    Layout Instance:    avD12_1  rphpoly

    r 2000 vs 11.0191 differs by 99.449%
    Schematic Instance is the merged result of:  X0/R1 X0/R0
    Layout Instance is the merged result of:  avD12_1 avD12_2

    = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = (param 4)
    Schematic Instance: I6/R0  rphpoly
    Layout Instance:    avD12_12  rphpoly

    r 1000 vs 7.64179 differs by 99.2358%

    ==========================================================================[DAC]
    ====== Summary of Errors ======================================================
    ===============================================================================

    Schematic  Layout     Error Type
    ---------  ------     ----------
     13         13        Bad Initial Net Bindings
     16         16        Bad Matched Nets
     -          7         Unmatched Internal Nets
     1          1         Matched Instances with Bad Net Connections
     1          45        Unmatched Instances
     4          4         Parameter Mismatches for Instances

    • Post Points: 20
  • Mon, Aug 27 2012 5:24 PM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,060
    • Points 16,080
    Re: LVS not running Reply

    Hi Sarvani

    No special setup is needed for Assura hierarchical LVS. From the cls file, it looks like the net mismatches might be due to the inability to combine parallel spcnmos and spcpmos devices. Perhaps you can check the compare rules file to see if appropriate mergeParallel cmds are present for these devices.

    By the way, actually it is really better for you to upload the cls file as an attachment and not cut and paste into the forum post because it makes the post very long and hides your question among the other info. This discourages other forum users from reading the post and helping you.  : )

    Best regards
    Quek

    • Post Points: 5
  • Mon, Aug 27 2012 5:26 PM

    • Quek
    • Top 10 Contributor
    • Joined on Wed, Oct 14 2009
    • Singapore, 00-SG
    • Posts 1,060
    • Points 16,080
    Re: LVS not running Reply

    Hi Sarvani

    One more point, this question should be posted to the CIC forum and not this SKILL forum. : )

    Best regards
    Quek

    • Post Points: 5
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Started by Sarvani at 28 Jun 2012 11:54 PM. Topic has 8 replies.