Hope every one is doing fine with their designs.
Can someone please help me with the following issue.
I was trying to generate cdb files using .cdl model and .scs model.
My .cdl model contains the netlist for the cells(lvs netlist) and .scs model contains the transistors and their parameters. But when I tried to use make_cdb, I'm getting an error from the tool saying that the cell doesn't contains any transistors. I checked the cell, it is a clock mux cell and it contains the transistors and the transisor defenition is in the .scs file as well.
can someone help me sort out the issue. If you need the .cdl file and .scs model for the purpose I can upload it. Please let me know if anyone can help.