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 Power Breakdown (sequential, combinational, I/O) report for hierarichal design 

Last post Mon, Jun 4 2012 8:02 AM by AliShami. 0 replies.
Started by AliShami 04 Jun 2012 08:02 AM. Topic has 0 replies and 1139 views
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  • Mon, Jun 4 2012 8:02 AM

    • AliShami
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    • Joined on Tue, Sep 2 2008
    • Posts 3
    • Points 45
    Power Breakdown (sequential, combinational, I/O) report for hierarichal design Reply

    I have a big reconfiguration design  which consists of a number of homogeneous tiles. I have mapped few algorithms on it. These algorithms when mapped do not consume all the tile in the design. I want to do power analysis on only these tiles which are being used.

     What I am looking for is, combinational power, sequentinal power, and I/O power. I do get such power breakdown if I used report_power at toplevel, but then this power report includes these tiles which are not being used. If I add -hierarchy switch then I only get Internal, Switching and leakage power without the break down that how much is being consumed by clock or combinational circuit.

     I am using VCD files for providing the switching activities. Anyhelp to solve this problem will be appreciated. 

     Regards/

    • Post Points: 5
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Started by AliShami at 04 Jun 2012 08:02 AM. Topic has 0 replies.