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 Unwanted "X" coming during re-simulation with vector 

Last post Wed, May 30 2012 10:39 PM by dhanash. 0 replies.
Started by dhanash 30 May 2012 10:39 PM. Topic has 0 replies and 2983 views
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  • Wed, May 30 2012 10:39 PM

    • dhanash
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    • Joined on Wed, May 30 2012
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    Unwanted "X" coming during re-simulation with vector Reply

    Hi,

    We are creating vectors with vcd files. If we re-run the simulation we are seeing few "X" on the signals which in turn causing simulation fail.

    Location of signal going "X" is,

    At the synchronizer input we are seeing logic high input for two clocks, for the first cycle synchonizer is able to give correct output but for second clock instead of giving logic high output we are getting X .

     

    • Post Points: 5
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Started by dhanash at 30 May 2012 10:39 PM. Topic has 0 replies.