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 Timing checks in ncsim 

Last post Fri, May 18 2012 11:51 AM by tpylant. 1 replies.
Started by MTP3 16 May 2012 11:27 AM. Topic has 1 replies and 4564 views
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  • Wed, May 16 2012 11:27 AM

    • MTP3
    • Not Ranked
    • Joined on Tue, Jun 7 2011
    • Posts 15
    • Points 195
    Timing checks in ncsim Reply

    HI!

    I am new to using ncsim and all so please excuse for simplistic questions, so anyways I want to simulate a state machine made up of DFFs (with no reset) and some logic gates. When I try to simluate the design electronically everything works fine but if use verilog descriptions of standard library cells (provided by the vendor) I get these X all along as everything connected to the DFFs has an X state.

    Is there any way to feed all the nodes some crap data (that is ofrced on them for like 10 clock periods and then deasserted)?

    My second question, is there anyway of disabling timing checks using ncsim. I am using ams simulator from ADE in cadence IC6.15. I already tried the option simulation->options->ams simulator->timing-> No timing checks but that doesn't help. 

    • Post Points: 20
  • Fri, May 18 2012 11:51 AM

    • tpylant
    • Top 50 Contributor
    • Joined on Fri, Jul 11 2008
    • Austin, TX
    • Posts 135
    • Points 2,030
    RE: Timing checks in ncsim Reply
    1.       Use the “irun –ncinitialize” or “ncsim +ncinitialize” command to initialize all registers.

    2.       Use the “notimingcheck” switch.

    Tim
    • Post Points: 5
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Started by MTP3 at 16 May 2012 11:27 AM. Topic has 1 replies.