Hello all,Sorry I posted topic to System Design and Verification also.
I am trying to learn how to simulate Verilog design. I import verilog code to design with Verilog-In, generated the schematic, functional and netlist. Now I want to use NC-Verilog to Compile, Elaborate and Simulate design. From the Schematic Editor > Launch > Simulation > NC-Verilog I run Verilog Environment.
Problem is with Simulation Setup form and NC-Verilog Executable field, which is not blank, but Verilog Integration says It is. The field is "ncxlmode". I didn't find ncxlmode in my cadence instalation. Should it be binary file and be installed with cadence? If, then what package contains this binary? I can not continue due to this error. Can anyone help me with this issue? The all problem is in Print-screen at:
I use IC18.104.22.1680.6, installed also MMSIM10.11, RC10.1, EDI10.1 on CentOS6.
Thank you very much in advance,