I'm trying to figure out a way to give my packaged classes indirect access to tasks that are declared as hierarchical-pahs.
Basically, I need a standard class definition that can access multiple instances of some module-instance within my testbench. Example:
endmodule : legacy_module_1
endmodule : testbench
// cls_1 needs ability to call instace_*.task_x();
endclass : cls_1
...classes in packages cannot contain hierarchical-references to anything outside of the package (so that rules out the easiest route.)
Next, I thought I would create an SV-interface, then declare extern tasks/functions inside the interface (i.e. 'proxy tasks', which then call instance_*.task_x() ) And create interface-ports on legacy_module_*, as hookup points.
But IUS 11 doesn't support it:
extern task x;
ncvlog: *E,SVNIMP (ptclass2.sv,3|11): SystemVerilog construct not yet implemented: extern tasks within an interface.
I also tried the alternate approach of 'importing' a task inside a modport declaration, but it seems IUS11 doesn't support that either.