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 TIE-HI and TIE_LO cells  

Last post Fri, Jul 20 2012 2:25 AM by Ganga111AtFPS. 8 replies.
Started by vedamrit 05 May 2012 12:11 AM. Topic has 8 replies and 4263 views
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  • Sat, May 5 2012 12:11 AM

    • vedamrit
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    TIE-HI and TIE_LO cells Reply

    Hi 

    Can we use VDD and VSS in place of TIE-HI and TIE-LO cells as they are logically equal .  

     

    Regards

    Amrit  

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  • Mon, May 7 2012 7:57 AM

    • diablo
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    • fargo, ND
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    Re: TIE-HI and TIE_LO cells Reply
    No. VDD/VSS if tied directly to gate of NMOS/PMOS, noise in the power supply may turn on the gate. This effect is mitigated by using special cells like TIEHI and TIELO that prevent the MOS from inadvertently turning on with power/ground bounce.
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  • Mon, May 7 2012 11:52 AM

    • tstark
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    Re: TIE-HI and TIE_LO cells Reply

    Don't some vendors allow direct VDD/VSS connections?

    I'm not a layout guy, so I'm not sure how this is handled electrically (diodes, caps, etc.) but I've seen it before. Maybe some vendors allow but risk the noise issue?

     

    tstark

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  • Mon, May 7 2012 9:03 PM

    • vedamrit
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    Re: TIE-HI and TIE_LO cells Reply

    Whether this is appicable for 90nm and 130 nm also or we are using its for 65, 45 or 28nm only .

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  • Mon, Jun 11 2012 6:33 AM

    • selvam27
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    Re: TIE-HI and TIE_LO cells Reply
    I tried this in 45nm and 130 nm ,direct connections of VDD/VSS instead of TIE-HI/TIE-LO is supported and it does't create any lvs issues
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  • Wed, Jul 4 2012 8:46 PM

    • Amare
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    Re: TIE-HI and TIE_LO cells Reply

    We ever had this kind of direct connection in our 0.18um chips.

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  • Wed, Jul 18 2012 2:51 AM

    • Ganga111AtFPS
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    Re: TIE-HI and TIE_LO cells Reply

    Hi diablo,

    How to make a TIE-HI or TIE-LO cells to drive constant 1-logic or constant 0-logic electrically?

    To what terminals we will connect VDD/VSS nets ?

    Thanks

    Gangadhar

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  • Wed, Jul 18 2012 7:37 AM

    • diablo
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    Re: TIE-HI and TIE_LO cells Reply

    TIE-HI and TIE-lo cells are already tied to constant 1-logic and costant 0-logic respectively.  

    To connect gates that are driven to constant 1 or 0 to tie cells, in RTL compiler there is command 

     'insert_tiehilo_cells -hi TIEHI_A7TULL -lo TIELO_A7TULL -all -maxfanout 20 -verbose'

    To have global net connectivity physically, in Encounter you will have to run  

    globalNetConnect VSS     -type tielo -inst * -module {} -override -verbose
    globalNetConnect VDD     -type tiehi -inst * -module {} -override -verbose

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  • Fri, Jul 20 2012 2:25 AM

    • Ganga111AtFPS
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    Re: TIE-HI and TIE_LO cells Reply

    Thank you..

    • Post Points: 5
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Started by vedamrit at 05 May 2012 12:11 AM. Topic has 8 replies.