I am completely new to pattern generation using ET. My aim is to generate STIL patterns for RAM retention test of a uC device.
I believe that the most important command of ET in this regard is the 'create_embedded_test'. I am using the following.........
et -e create_embedded_test \
Now if I generate the patterns using the above command (of course other commands such as build_model, build_faultmodel & write_vectors will be executed in order) and then simulate the patterns, I see that my RAM is first written and then read (as percheckerboard_retention algo.) multiple times and then simulation ends.
But I want to do something more and this is where my problem starts.
I would like to power down my device which contains this RAM, basically to a voltage lower than the recommended supply voltage, then power-up the device and then recheck whether the RAM retains all the data that was written into it previously.
I don't know how to do this using ET acripts. Some reading into Cadence Help has indicated that I can use the command 'splitretentionpatterns=yes', that will allow user intenvention to insert custom action (in my case to power down the device, pause for some time and then power up the device) and continue with the tests. I copy the following directly from Cadence Help......
"If createpatterns=production is combined with splitretentionpatterns=yes the pattern allows for user intervention at the points in the retention algorithm where the test pauses"
I have no clue on how to use the ET commands to achieve the action described above. The Cadence Help is also not clear to me.
Has anyone done some similiar RAM retention test using ET? Any type of help/suggestion on how to proceed will be very helpful.
Thanks in advance,