I think that understand the basic flow, but these is one issue that causes issues.
I have the current post layout netlist G1 - this is "golden"
I generate a new netlist using RTL compler G2 - this is "revised".
I can compare G1 and G2 and generate patch files using conformal ECO.
There is one major issue, and it is not clear how to handle. G1 contains clock, buffer and additional scan ports, which means that there are additional ports on the module of interest.When I look at the generated netlist (G3), non of these extra ports are used.e.g. The clock is not taken from the clock tree port, but from the origincal (pre P&R) clock net.
I have been looking at the ignore input/output command, but these don't seem to make any difference.
Am I overlooking some obvious switch on one of the commands?