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 RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement 

Last post Thu, Mar 29 2012 2:37 AM by mamsadegh. 0 replies.
Started by mamsadegh 29 Mar 2012 02:37 AM. Topic has 0 replies and 2485 views
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  • Thu, Mar 29 2012 2:37 AM

    • mamsadegh
    • Not Ranked
    • Joined on Wed, Jun 22 2011
    • Bologna, Bologna
    • Posts 13
    • Points 170
    RTL Compiler - read_tcf - Cannot read TCF file when using Generate verilog statement Reply

    Hi

    Here I am describing an issue that I have seen using RC 10.1 and NCSim 9. 

    In order to estimate power with RC we need to read circuit switching activity as TCF/VCD files.

    As of my tests the VCD reader engine of RC 10.1 has bugs. So, i don't use it at all. 

    For reading TCF file, 

    if I use "generate" verilog statement, for instantiating a module several time, then when I simulate the design and create TCF file, then when I try to read the TCF inside RC , i will see this message and read_tcf stops working. 

    "unmatched open brace in list"

    so actually, the tool can not read the TCF file produced by NCSim. 

    on the NCSim side the simulation is fine and it goes until end with no problem. 

    Now, if I remove the "generate" verilog statement and i do instantiation manually,

    every thing works fine. 

     

    M.S.Sadri.
    • Post Points: 5
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Started by mamsadegh at 29 Mar 2012 02:37 AM. Topic has 0 replies.