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 How to set_current_module in RTL Compiler?? 

Last post Mon, Dec 16 2013 11:39 PM by jojo57006. 10 replies.
Started by archive 07 Jul 2007 01:00 PM. Topic has 10 replies and 7622 views
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  • Sat, Jul 7 2007 1:00 PM

    • archive
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    How to set_current_module in RTL Compiler?? Reply

    Hi all,

    I need to perform synthesis of a sub-block of the design. And then merge it with the top design.
    I am using RTL Compiler.

    In pks or build gates this was simple, we had the command set_current_module .. and one can then perform synthesis on a subdesign.

    There seems to be no direct equivalent of set_current_module in RTL Compiler.

    I found one command in RTL Comiler, derive_environment.
    This promotes a subdesign to a topdesign.
    So in design database we will now have
    /designs/topdesign
    /designs/subdesign_promoted_top

    The synthesis which I perform on /designs/subdesign_promoted_top is now independent of actual topdesign.

    This  works. But how can I later merge the
    /designs/subdesign_promoted_top
    into
    /designs/topdesign ??

    I see no way to do this in the userguide!

    Can someone help me?

    Thanks in advance,
    Pradeep


    Originally posted in cdnusers.org by spveer
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  • Sat, Jul 7 2007 9:27 PM

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    RE: How to set_current_module in RTL Compiler?? Reply

    Hi Pradeep,

    Try the following:

    edit_netlist new_instance -name /designs/subdesign_promoted_top /designs/topdesign

    There are more options for "edit_netlist new_instance" in the manual

    Regards,
    Max


    Originally posted in cdnusers.org by Stalker
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  • Sat, Jul 7 2007 9:29 PM

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    RE: How to set_current_module in RTL Compiler?? Reply

    Sorry, tipo:
    edit_netlist new_instance -name SUBDESIGN_INST_NAME /designs/subdesign_promoted_top /designs/topdesign


    Originally posted in cdnusers.org by Stalker
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  • Sun, Jul 8 2007 12:06 AM

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    RE: How to set_current_module in RTL Compiler?? Reply

    Thanks Stalker,

    I will try this tomorrow, when I am in office..

    But what should I do with the existing subdesign in the topdesign..?
    will that be overwritten?

    Or should I first remove the existing subdesign, and then create a new instance using the subdesign_promoted_top?

    Can you please tell me if possible, about how merging takes place...

    Thanks,
    Pradeep


    Originally posted in cdnusers.org by spveer
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  • Sun, Jul 8 2007 12:23 AM

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    RE: How to set_current_module in RTL Compiler?? Reply

    You can continue working with you topdesign as usual, the only thing, that you can't omit the design name in the commands, for example:
    write_hdl topdesign > top.v
    and not
    write_hdl > top.v
    I don't know exactly how the new instance is linked, but I think the subdesign_promoted_top is needed for correct work.


    Originally posted in cdnusers.org by Stalker
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  • Mon, Jul 9 2007 1:15 AM

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    RE: How to set_current_module in RTL Compiler?? Reply

    Hi Max,

    I tried using this...
    edit_netlist new_instance -name SUBDESIGN_INST_NAME /designs/subdesign_promoted_top /designs/topdesign

    now on the topdesign I have an unconnected instance in the hierarchy,  called SUBDESIGN_INST_NAME

    If I try to optimize, since this instance is unconnected, and not driving any ports, the instance is removed by synthesis.

    ------
    I also tried the following:

    The hierarchy looks like this:
    /designs/topdesign/instances_hier/xxxx
    /designs/topdesign/instances_hier/subdesign  ----- this is promoted to subdesign_promoted_top
    /designs/topdesign/instances_hier/SUBDESIGN_INST_NAME  ---- this is subdesign_promoted_top copied back into topdesign


    now I removed subdesign
    rm /designs/topdesign/instances_hier/subdesign

    So the hierarchy now looks like this:
    /designs/topdesign/instances_hier/xxxx
    /designs/topdesign/instances_hier/SUBDESIGN_INST_NAME  ---- this is subdesign_promoted_top copied back into topdesign

    then I have run 'synthesize'... But however the tool sees /designs/topdesign/instances_hier/SUBDESIGN_INST_NAME, not driving any ports and optimizes it away.... but doesnt link it to topdesign!! :(

    ----

    I am still not sure, how to link the designs....


    Originally posted in cdnusers.org by spveer
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  • Mon, Jul 9 2007 7:22 AM

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    RE: How to set_current_module in RTL Compiler?? Reply

    Hi Pradeep,

    have you tried the change_link command. I have used this in the past in a similar flow with pretty good success. I think the key is that the pin names have to match.

    gh-


    Originally posted in cdnusers.org by grasshopper
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  • Mon, Jul 9 2007 8:03 AM

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    RE: How to set_current_module in RTL Compiler?? Reply

    Hi gh,

    yes,  change_link works...!
    i was just trying that and got ur mail too :)

    thanks n regards,
    pradeep


    Originally posted in cdnusers.org by spveer
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  • Mon, Dec 16 2013 8:35 AM

    • jojo57006
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    Re: How to set_current_module in RTL Compiler?? Reply

    Hello, 

    Me too I am trying to synthesize subdesigns because my vhdl code is too big. So, I need to put to a top-level every instance of my design and so on use the command derive_environment.

    Please can you help me to use this command. Where I write :
    rc :> derive_environment /designs/my_top_design/instances_hier/my_subdesign_to_put_to_top_level
    the terminal is block !!

    This command take a long time or there is a problem with it ? 

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  • Mon, Dec 16 2013 8:49 AM

    • grasshopper
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    Re: How to set_current_module in RTL Compiler?? Reply

    How big is  /designs/my_top_design/instances_hier/my_subdesign_to_put_to_top_level ?

    What exactly is your goal ? Can you describe what your flow is ?

     

    gh-

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  • Mon, Dec 16 2013 11:39 PM

    • jojo57006
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    Re: How to set_current_module in RTL Compiler?? Reply

    My goal is to make the low power multi vdd synthesis of my design : design/top_rs232

    I have 200 000 gates to synthesize and I work on the server of my school. I can't make the synthesis directly because of this server so I want to elaborate all the design and synthesize each blocks separately. After I will read all the .v file and redo the synthesis which now the server can support.   

    • Post Points: 5
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Started by archive at 07 Jul 2007 01:00 PM. Topic has 10 replies.