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 Ideas for integrating a full-custom designed layout with a semi-custom designed microprocessor. 

Last post Fri, Mar 23 2012 2:04 PM by Thommandram. 0 replies.
Started by Thommandram 23 Mar 2012 02:04 PM. Topic has 0 replies and 2012 views
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  • Fri, Mar 23 2012 2:04 PM

    Ideas for integrating a full-custom designed layout with a semi-custom designed microprocessor. Reply

    Hello,

    I have verilog codes - (of a microprocessor design.), tell me a way to do the logic and physical synthesis which satisfies the below conditions:

    I created register file/ RAM layout in cadence virtuoso. These register files are created with a novel architecture, and I want to add these in to the microprocessor design which is mentioned before.

    Please note that I am not creating memory or a RAM for the microprocessor in verilog codes. I am creating a custom-designed layout in cadence virtuoso to create the RAM.

    I want to know how to integrate the two design layouts together. Any suggestion/ ideas are welcome.

    1 easy method which comes to mind : DO the logic synthesis in Cadence RTL Compiler in regular fashion and then, while creating the layouts in SOC Encounter, leave a seperate space in the floorplan for the custom designed layout. So that, it can be attached later.

    Does this idea work? Kindly help me with an optimized design flow solution . please!!! 

    • Post Points: 5
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Started by Thommandram at 23 Mar 2012 02:04 PM. Topic has 0 replies.