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 I am using FreePDK45nm library. I couldn't synthesise a register file. 

Last post Wed, Mar 28 2012 6:07 AM by grasshopper. 1 replies.
Started by Thommandram 21 Mar 2012 10:01 AM. Topic has 1 replies and 2157 views
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  • Wed, Mar 21 2012 10:01 AM

    I am using FreePDK45nm library. I couldn't synthesise a register file. Reply

    Hello,

    I am doing a microprocessor design. Sap-1 architecture. I've attached the verilog codes of this microprocessor here.

    The problem is.. I couldn't finish the logic synthesis of  the processor. During synthesis in the Cadence RTL compiler-Physical, the the synthesis stops at one point. At this point, the gui window status bar shows "computing design", and the terminal window shows "accessing module mem16K or reading varible mem" But the software gets hanged at this point.

    The problem maybe with the memory/register file structures, I'm not sure. I want to know whether the library FreePDK45nm might be the problem (I've tried a Nangate library too!, it isn't working with that either.). 

    Do you think the FreePDK45nm has the correct memory cells to implement a register file? If so, What else would be the problem in synthesizing a register file.

     

     

    code for the memory block or the RAM in the microprocessor.

     

    */

    module mem16K(data, address, CS, WE, OE);

      parameter wordSize = 8;

      parameter addressSize = 4;

     

      inout [wordSize-1:0] data;

      input [addressSize-1:0] address;

      input CS, WE, OE;

     

      reg [wordSize-1:0] dataReg;

      reg [wordSize-1:0] memory [0:1<<addressSize];

     

      // attach a tristate buffer to the databus

      // if OE is active(low), connect datawires to the dataRegisters

      // if OE is inactive(high), set datawires to high impedance for input

     

      assign data = (!OE && WE && !CS)?dataReg:8'hzz;

     

      // the reason cs is not put in the condition is

      // internal wires are in accordance with databus

      // but the data is not stored in memory so no problem

     

      initial

      begin

    /* execution of a small program */

    memory[0] = 8'h09; // LDA 9H

    memory[1] = 8'h1A; // ADD AH

    memory[2] = 8'h1B; // ADD BH

    memory[3] = 8'h2C; // SUB CH

    memory[4] = 8'hE0; // OUT

    memory[5] = 8'hF0; // HLT

     

      // dataReg = 8'h00;

    // Instructions must be stored here before running SAP1

    // memory[0] = 8'b00001011; // LDA 08H ( ie: load contents from memory loc. 8 (B8) to acc)

    // memory[1] = 8'b11100000;

    // memory[2] = 8'b00011000;

    // memory[3] = 8'b11100000;

    //memory[2] = 8'b00001010;

    //memory[3] = 8'b00001011;

    //memory[2] = 8'b00011001; // ADD 09H 

    //memory[2] = 8'b00011011;

     

    // data contents of memory

    memory[9] = 8'h01;

    memory[10] = 8'h02;

    memory[11] = 8'h03;

    memory[12] = 8'h04;

     

      end

      

      always @(WE or OE or CS)

      begin

        // incase of active(low) CS and active(low) WE

        if (!CS && !WE)  

        begin

          #1;

          memory[address] = data;

    //      $display(data);

        end

      end

     

      always @(WE or OE or CS)

      begin

          if (!OE && !CS && WE)

            dataReg = memory[address];

      end

    endmodule

     

     

    do you see any problem with this block? But I am able to simulate this code in the xilinx ise.. I'm just not able to do the synthesis.. help!! 

     

    Thanks in advance. 

    • Post Points: 20
  • Wed, Mar 28 2012 6:07 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
    • Posts 242
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    Re: I am using FreePDK45nm library. I couldn't synthesise a register file. Reply
    HI Thommandram, looks like you are reading the behavioral model of the register files which is intended for your functional simulations. For synthesis, you need a liberty model (.lib) for them gh-
    • Post Points: 5
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Started by Thommandram at 21 Mar 2012 10:01 AM. Topic has 1 replies.