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 RTL Compiler -- clock latency 

Last post Wed, Mar 28 2012 6:10 AM by grasshopper. 1 replies.
Started by amitram 17 Mar 2012 01:31 PM. Topic has 1 replies and 2396 views
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  • Sat, Mar 17 2012 1:31 PM

    • amitram
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    • Joined on Sat, Mar 17 2012
    • Pune, Maharashtra
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    RTL Compiler -- clock latency Reply

    Hi,

    1.  Can someone please explain what is the exact meaning of clock latency.

    2. What is the meaning of the following RC scripts

         1. path_adjust   -from  clk2  -name latency1  -delay  -30

         2. path_adjust   -to   clk2    -name latency2   -delay   30

    where :-   one pin named "clk2" is the internal clock source pin of the PLL and the other clk2 is the clock port of some block.

    why is the latency specified in terms of negative time (-30ps). ? 

     

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  • Wed, Mar 28 2012 6:10 AM

    • grasshopper
    • Top 25 Contributor
    • Joined on Thu, Jul 17 2008
    • Chelmsford, MA
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    Re: RTL Compiler -- clock latency Reply
    Hi Amitram, there is a nice write-up over here http://www.edaboard.com/thread130000.html I would go further to say that while modelling latency using path_adjust works, there is an SDC command set_clock_latency intended for exactly that purpose which is probably a better way to model. path_adjust positive and negative simply means adjusting the path by adding or subtracting a given delay number hope this helps, gh-
    • Post Points: 5
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Started by amitram at 17 Mar 2012 01:31 PM. Topic has 1 replies.