I'm desinnig a Time to digital converter and I would like to simulate the jitter of a driven buffer having a rising time of 350 ps.
In my schematic, the buffer is driven by vpulse (ideal CLK @ 2 MHz) and I would like to simulate his output jitter.
My setting of pss simulation is as follow:
Beat frequency : auto Calculate, wich is 2 MHz
Number of harmonic : 10
Accuracy : Moderate
Now, my problem is in setting the pnoise analysis
1) how we set the output frequency sweep range?
2) Maximum of side band : The jitter depends strongly on this value. So how can we set it ?
3) In the main Form, when we plot the Jee, we have to set the integration limits : How can we set this.