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 use generated clock to sample the logic value driven by main clock. 

Last post Tue, Mar 6 2012 6:59 AM by TAM1. 2 replies.
Started by phoenixson 06 Mar 2012 01:59 AM. Topic has 2 replies and 2785 views
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  • Tue, Mar 6 2012 1:59 AM

    • phoenixson
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    • beijing, Beijing
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    use generated clock to sample the logic value driven by main clock. Reply
    HI, all
    Now I encountered one problem when I do RTL simulation. there is one main clock named 'main_clk"  in the design, and another clock named 'clk_div2' which is generated from 'main_clk', it is divided by two, I want to use 'clk_div2' to sample the logic signal driven by 'main_clk', but I found I can not get the correct value, it seems that 'clk_div2'  sampled the next cycle value, not the current one.  what causes that ?  but after synthesizing and building clock tree, the problem disappeared, why?
    Just do it.
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  • Tue, Mar 6 2012 2:07 AM

    • Shalom B
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    RE: use generated clock to sample the logic value driven by main clock. Reply
    Is the divided clock generated with a nonblocking assignment? It should be a blocking assignment.

    Shalom
    Shalom.Bresticker@intel.com
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  • Tue, Mar 6 2012 6:59 AM

    • TAM1
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    Re: RE: use generated clock to sample the logic value driven by main clock. Reply

    Do you have access to information on support.cadence.com? If so, there is an App-Note that explains why you should use a blocking vs. a non-blocking assignment in your clock tree. There are some other race condition issues that you can look for too.

     Race Conditions

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Started by phoenixson at 06 Mar 2012 01:59 AM. Topic has 2 replies.