Now I encountered one problem when I do RTL simulation. there is one main clock named 'main_clk" in the design, and another clock named 'clk_div2' which is generated from 'main_clk', it is divided by two, I want to use 'clk_div2' to sample the logic signal driven by 'main_clk', but I found I can not get the correct value, it seems that 'clk_div2' sampled the next cycle value, not the current one. what causes that ? but after synthesizing and building clock tree, the problem disappeared, why?
Just do it.