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 creating a schematic file from a netlist file 

Last post Thu, Aug 30 2012 3:54 AM by AKASHJ. 5 replies.
Started by SrinivasaL 10 Feb 2012 04:00 AM. Topic has 5 replies and 5255 views
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  • Fri, Feb 10 2012 4:00 AM

    • SrinivasaL
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    • Joined on Fri, Feb 10 2012
    • Posts 1
    • Points 20
    creating a schematic file from a netlist file Reply

    Hi,

    I am looking to create a skill program which could generate a schematic file from a given netlist file(present in text format).

    netlist will be more of digital gate instances connected together.

    Does anyone have idea or process how it can be done? A sample code would be great help.

     

    Thanks,

    Srinivasa

    • Post Points: 20
  • Fri, Feb 10 2012 4:49 AM

    Re: creating a schematic file from a netlist file Reply

    Srinivasa,

    Why would you want to write a SKILL program to do this? Both File->Import->Verilog and File->Import->SPICE (IC61) or File->Import->CDL (IC5141) will do this for you from different netlist formats.

    It seems a bit unnecessary reinventing a standard capability...

    Regards,

    Andrew.

    • Post Points: 20
  • Mon, Feb 20 2012 4:27 AM

    • ebecheto
    • Top 200 Contributor
    • Joined on Fri, Oct 10 2008
    • Villeurbanne, Rhone
    • Posts 39
    • Points 705
    Re: creating a schematic file from a netlist file Reply

    Hello Andrew,  hello Srinivasa,

    I had asked myselft one day if I should develop a netlist parser, without knowing it allready exist un Cadence. However, I dit not succeed in importing a simple spectre netlist with the spice In Import (IC6).

     I tried to import :  /soft/cadence/IC610/tools/dfII/samples/artist/OCEAN/opamp741Char/design/netlist

     But it fails, spiceIn.log issuing :        

     Master Cell: 'capacitor'.
            Master cell CDF data not found for 'sample.capacitor'
            Did not find 'basic.capacitor:symbol'.
            Did not find 'analogLib.capacitor:symbol'.
            Did not find ANALOG_TUT.capacitor:schematic.
    ERROR (SPICEIN-24): Spice In did not find the symbol view of the master cell 'capacitor' of the instance
    'c5' in the subcircuit 'opamp_g1'. Specify the reference library that has the symbol
    view of the master cell, or use device-mapping to map 'capacitor' to a different
    cell.

     Is there a tutorial that explainshow to use it? It seem simple, but for me it simply failled...


     

     

    • Post Points: 20
  • Mon, Feb 20 2012 4:41 AM

    Re: creating a schematic file from a netlist file Reply

    Did you try reading the documentation? You'll almost certainly need a device map and a reference library. I don't think there's a tutorial, but the documentation exists... the Help button on the File->Import-SPICE form takes you to the right manual.

    I think there are a number of solutions on this on Cadence Online Support. Here's a simple one - there are others.

    Andrew.

    • Post Points: 35
  • Mon, Feb 20 2012 7:05 AM

    • ebecheto
    • Top 200 Contributor
    • Joined on Fri, Oct 10 2008
    • Villeurbanne, Rhone
    • Posts 39
    • Points 705
    Re: creating a schematic file from a netlist file Reply

     Thanks, It shows me that I indeed have to map:

    devselect := resistor res
    devselect := capacitor cap

     I allready added analogLib to the 'Reference Library List', but I added 'basic' too, which seams to be not a good references library for capacitor.

    Thanks it worked.

    • Post Points: 5
  • Thu, Aug 30 2012 3:54 AM

    • AKASHJ
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    • Joined on Thu, Aug 30 2012
    • Posts 1
    • Points 5
    Re: creating a schematic file from a netlist file Reply

     I haveaccidently deleted my schematic File (sch.cdb) but i have the netlist file 

     I tried to use File->Import->CDL In

    I dont know exactly how to do it ........But i tried and i didnt specify any thing in Parameter File and Device map File

    I got ni.log files Which was as below

     
    ############################################

    Reference Libraries...
    AKASH_JOSHI
    UMC_18_CMOS
    basic
    analogLib
    avTech
    AKASH_JOSHI
    ###################################

    0 subckt(s) found in the netlist file.

     

     TOTAL CELLS #: 0



           *************************     
           ******   SUMMARY   ******     
           *************************     



        CELL                           TERMINAL #    NET #      INSTANCE #    
      -----------------------------------------------------------------------------
    home/anita/simulation/GRO_TDC/spectre/schematic/netlist INPUT

      CIRCUIT FILE INPUT AND PROCESSED
    *WARNING* LIB mtech11 from File /home/anita/umc_work/cds.lib Line 5 redefines
    LIB mtech11 from the same file (defined earlier.)
    *WARNING* The directory: '/home/anita/umc_work/mtech11' does not exist
        but was defined in libFile '/home/anita/umc_work/cds.lib' for Lib 'mtech11'.
    *WARNING* The directory: '/home/anita/cad_work/umc_work/my_lib' does not exist
        but was defined in libFile '/home/anita/umc_work/cds.lib' for Lib 'my_lib'.
    What do i do...........or any you suggest any better way

    pl help

     

    • Post Points: 5
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Started by SrinivasaL at 10 Feb 2012 04:00 AM. Topic has 5 replies.