The question may be quite trivial for many out in this forum .. .i would like to discuss more of a methodology related question with respect to RC tool usage ...for synthesis .!!!
What are the several Synthesis flows recommended by RTL compiler?
Not all designs are computational intensive datapaths, Few are intensive datapaths, Few are Clock intensive paths( more of clock path generation) and few designs are Memory intensive..
What is the best way to deal with each type of the Designs interms of methodologies .. ? how do we ensure that we have optimized the best possible way? How to verify for any improvements in the design QoR, timing, area & power...?
Apart from CG gating, what other techniques do we employee to target the low power synthesis?
I also found that Multi-Vt optimization in synthesis is not a good idea from the tool perspective as this is not giving a good results?
Usually, DC provides a lot of template scripts targetting for timing, area & power separately? Any such tricks available in RTL compiler as well??
Please share your views !!