Home > Community > Forums > Logic Design > sub architecture selection

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 sub architecture selection 

Last post Sat, Jan 20 2007 9:54 AM by archive. 13 replies.
Started by archive 20 Jan 2007 09:54 AM. Topic has 13 replies and 3193 views
Page 1 of 1 (14 items)
Sort Posts:
  • Sat, Jan 20 2007 9:54 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    sub architecture selection Reply

    In a block with deep asynchronous logic, there are some multiplier stages. I synthesized this block stand-alone and "report datapath" does not show me a multiplier architecture for it. Then I have applied following pragma:

    assign some_prod[24:0] = {15'h0,some_term1[9:0]} * /* cadence sub_arch booth */ {{10{some_term2[14]}},some_term2[14:0]};

    Please note the sign extension for the 2nd term.

    Neither elab nor "synthesize -to_generic -effort high" shows me an information about this setting. The results with pragma above are without pragma are the same, ie. pragma does not seem to have an effect.

    set_attr user_sub_arch booth [find / -design my_design]

    does not work, because the attribute can be assigned only to subdesigns.

    The reason why I do this experiment in a stand-alone synthesis is that the runtime of the complete system takes ca. 6 hours.

    RC is v06.20-p003_1.

    Can the HDL coding style affect the mechanism of inferring synthetic operators?


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Jan 23 2007 12:16 PM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Sorry for my stupid posting again. It is crystal clearly stated in the cdsdoc in which conditions and which RTL coding enables automatic architecture inferring.


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Mon, Nov 19 2007 8:51 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    I still have an issue in this subject. RTL code pragmas for architecture selection do not seem to be working. Here is an example. Following is a multiplier kernel:

    module mult_kernel #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output [WIDTH_A*WIDTH_B-1:0] prod
    );

    assign prod = terma * /* cadence sub_arch booth */ termb;

    endmodule

    Following block is top-level of multiplier kernel:


    module mult_prm #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input clk_data,
    input rst_data_n,
    input enable,
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output reg [WIDTH_A*WIDTH_B-1:0]prod
    );

    reg [WIDTH_A-1:0] terma_int;
    reg [WIDTH_B-1:0] termb_int;

    always @(posedge clk_data)
    if (!rst_data)
    begin
    terma_int <= 0;
    termb_int <= 0;
    end
    else if (enable)
    begin
    terma_int <= terma;
    termb_int <= termb;

    wire [WIDTH_A*WIDTH_B-1:0] prod_int;
    mult_kernel #(WIDTH_A, WIDTH_B) my_mult (terma_int, termb_int, prod_int);

    always @(posedge clk_data)
    if (!rst_data_n)
    prod <= 0;
    else if (enable)
    prod <= prod_int;

    endmodule

    Although I have specified the architecture selection as "booth", RTL Compiler does not even generate an informative message about that the tool recognized the attribute setting.

    The design above is very simple, as you see. I have done the things above exactly as it is stated in Datapath Optimization part of the Datapath Synthesis in Encounter RTL Compiler chapter.

    However RTL Compiler generate a non_booth architecture.
    I am using special licenses for RTL Compiler. Is this booth feature so difficult to set it up?


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Mon, Nov 19 2007 9:18 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Try "report datapath" after elab (need to set_attr hdl_track_filename_row_col true before elab), it will show:

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea Line Col Filename
    -----------------------------------------------------------------------------------------------------------------
    mult_unsigned my_mult/mul_45_21 * unsigned very_fast/booth(u) 5x10 15 9089.71 45 21 mult.v
    -----------------------------------------------------------------------------------------------------------------


    Originally posted in cdnusers.org by synthman
    • Post Points: 0
  • Tue, Nov 20 2007 7:57 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    No, "report datapath" gives me a non-Booth architecture.

    I have RTL Compiler v07.10-s009_1.

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea Line Col Filename
    -----------------------------------------------------------------------------------------------------------------------
    mult_unsigned my_mult/mul_11_21 * unsigned very_fast/non_booth 5x10 15 3381.38 11 21 mult_kernel.v
    -----------------------------------------------------------------------------------------------------------------------


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Nov 20 2007 8:32 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Hi Sporadic Crash,

    I have never used this pragma and, to be honest, I am not much of a fan of them but this one definitely peeked my curiosity. I made some minor mods to the code you posted since there were a couple typos. Hopefully this is not the cause of my success. I ran RC v07.10-s009_1 and the following simple script

    set_attr library tutorial.lbr
    read_hdl -v2001 booth.v
    elab
    report datapath
    synth -to_mapped
    report datapath

    both report datapath displayed booth. I tried it without the pragma and it showed non-booth. Pretty cool !!!
    Though I have been brain washed :) and converted to the very_slow to very_fast approach RC uses. Makes my life easier . . .

    Here is the HDL I used which should be almost identical to the one you posted

    module mult_kernel #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output [WIDTH_A*WIDTH_B-1:0] prod
    );

    assign prod = terma * /* cadence sub_arch booth */ termb;

    endmodule

    module mult_prm #(
    parameter WIDTH_A = 5,
    WIDTH_B = 10
    ) (
    input clk_data,
    input rst_data_n,
    input enable,
    input [WIDTH_A-1:0] terma,
    input [WIDTH_B-1:0] termb,
    output reg [WIDTH_A*WIDTH_B-1:0]prod
    );

    reg [WIDTH_A-1:0] terma_int;
    reg [WIDTH_B-1:0] termb_int;
    wire [WIDTH_A*WIDTH_B-1:0] prod_int;

    always @(posedge clk_data)
    if (rst_data_n)
    begin
    terma_int <= 0;
    termb_int <= 0;
    end
    else if (enable)
    begin
    terma_int <= terma;
    termb_int <= termb;
    end // if (enable)

    mult_kernel #(WIDTH_A, WIDTH_B) my_mult (terma_int, termb_int, prod_int);

    always @(posedge clk_data)
    if (!rst_data_n)
    prod <= 0;
    else if (enable)
    prod <= prod_int;

    endmodule

    happy thanksgiving,
    gh-


    Originally posted in cdnusers.org by grasshopper
    • Post Points: 0
  • Tue, Nov 20 2007 8:53 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    No, I still *do not* have it:

    Elaboration tells me:
    Info : An implementation was inferred. [CWD-19]
    : The implementation '/hdl_libraries/GB/components/mult_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'MULT_UNS_OP' (pin widths: A=5 B=10 Z=15) at line 11 in the file 'booth.v'.
    Info : Sorted the set of valid implementations for synthetic operator. [CWD-36]
    : The implementations for the call to synthetic operator 'MULT_UNS_OP' (pin widths: A=5 B=10 Z=15) at line 11 in the file 'booth.v' will be considered in the following order: {'/hdl_libraries/GB/components/mult_unsigned/implementations/very_fast' (priority 1), '/hdl_libraries/GB/components/mult_unsigned/implementations/medium' (priority 1), '/hdl_libraries/GB/components/mult_unsigned/implementations/slow' (priority 1)}

    but then:

    Inferred components

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea Line Col Filename
    --------------------------------------------------------------------------------------------------------------------
    mult_unsigned_mbvp_l my_mult/mul_11_21 * unsigned slow/non_booth 5x10 15 1105.28 11 21 booth.v
    2qtv

    :) What is that now??

    1. read_hdl
    2. elaborate
    3. read_sdc
    4. synthesize -to_generic
    5. synthesize -to_mapped -no_incremental
    6. synthesize -to_mapped -incremental

    After each call of "synthesize" I generate "report datapath". NONE of them gives me a report about Booth architecture.




    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Nov 20 2007 9:10 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Hi Grasshopper,

    the distributed approach has an incremental tech mapping as you see. I cannot tell the reason for company reasons.
    I have removed the 4th part (generic synthesis) which leads that step 5 performs full synthesis. No, there is no change in the architecture.

    I think this selection happens during elaboration time. As you see, elab report tells me the architecture will be very_fast but report datapath tells me it is not. OTOH, RTL Compiler docs tell me that Booth arch is selected automatically only if WIDTH > 13. I don't have it here.

    Grasshopper, do you have specail Cadence env var or special attrib for that?


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Nov 20 2007 9:42 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Re-run with your script and out-of-the-box setup

    set_attr library tutorial.lbr
    set_attr information_level 9 /
    read_hdl -v2001 booth.v
    elab
    report data
    synth -to_gen
    report data
    synth -to_mapped -no_incr
    report data
    synth -to_mapped -incr
    report data

    and here is the output


    Cadence Encounter(R) RTL Compiler
    Version v07.10-s009_1 (32-bit), built Aug 8 2007

    ...

    Setting attribute of root '/': 'information_level' = 9
    Reading Verilog file 'booth.v'
    Elaborating top-level block 'mult_prm' from file 'booth.v'.
    Elaborating block 'mult_kernel_WIDTH_A5_WIDTH_B10' from file 'booth.v'.
    Info : An implementation was inferred. [CWD-19]
    : The implementation '/hdl_libraries/GB/components/mult_unsigned/implementations/very_fast' was inferred through the binding 'b1' for the call to synthetic operator 'MULT_UNS_OP' (pin widths: A=5 B=10 Z=15) at line 10 in the file 'booth.v'.
    Info : Sorted the set of valid implementations for synthetic operator. [CWD-36]
    : The implementations for the call to synthetic operator 'MULT_UNS_OP' (pin widths: A=5 B=10 Z=15) at line 10 in the file 'booth.v' will be considered in the following order: {'/hdl_libraries/GB/components/mult_unsigned/implementations/very_fast' (priority 1), '/hdl_libraries/GB/components/mult_unsigned/implementations/medium' (priority 1), '/hdl_libraries/GB/components/mult_unsigned/implementations/slow' (priority 1)}
    Done elaborating 'mult_prm'.

    ...

    Command: report datapath
    ============================================================
    Generated by: Encounter(R) RTL Compiler v07.10-s009_1
    Generated on: Nov 20 2007 12:32:41 PM
    Module: mult_prm
    Technology library: tutorial 1.0
    Operating conditions: typical_case (balanced_tree)
    Wireload mode: enclosed
    ============================================================


    Inferred components

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea
    -----------------------------------------------------------------------------------------------
    mult_unsigned my_mult/mul_10_21 * unsigned very_fast/booth(u) 5x10 15 594.75
    -----------------------------------------------------------------------------------------------

    ...

    ============================================================
    Generated by: Encounter(R) RTL Compiler v07.10-s009_1
    Generated on: Nov 20 2007 12:32:42 PM
    Module: mult_prm
    Technology library: tutorial 1.0
    Operating conditions: typical_case (balanced_tree)
    Wireload mode: enclosed
    ============================================================


    Inferred components

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea
    -----------------------------------------------------------------------------------------------
    mult_unsigned my_mult/mul_10_21 * unsigned very_fast/booth(u) 5x10 15 591.75
    -----------------------------------------------------------------------------------------------

    ...

    ============================================================
    Generated by: Encounter(R) RTL Compiler v07.10-s009_1
    Generated on: Nov 20 2007 12:32:46 PM
    Module: mult_prm
    Technology library: tutorial 1.0
    Operating conditions: typical_case (balanced_tree)
    Wireload mode: enclosed
    ============================================================


    Inferred components

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea
    ------------------------------------------------------------------------------------------
    mult_unsigned my_mult/mul_10_21 * unsigned slow/booth(u) 5x10 15 379.50
    ------------------------------------------------------------------------------------------

    ...

    ============================================================
    Generated by: Encounter(R) RTL Compiler v07.10-s009_1
    Generated on: Nov 20 2007 12:32:46 PM
    Module: mult_prm
    Technology library: tutorial 1.0
    Operating conditions: typical_case (balanced_tree)
    Wireload mode: enclosed
    ============================================================


    Inferred components

    Module Instance Operator Signedness Architecture Inputs Outputs CellArea
    ------------------------------------------------------------------------------------------
    mult_unsigned my_mult/mul_10_21 * unsigned slow/booth(u) 5x10 15 379.50
    ------------------------------------------------------------------------------------------

    ...

    Sorry but did not do anything special I am aware of

    good luck,
    gh-


    Originally posted in cdnusers.org by grasshopper
    • Post Points: 0
  • Tue, Nov 20 2007 9:58 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Grasshopper,

    your technology library and constraints might be a little more relaxed than by me.

    On the other hand, does RTL Compiler generate any message about your inline pragma coded in RTL code? (cadence sub_arch booth).

    As we see in the reports above, RTL Compiler changed the sub-architecture selection from very_fast/booth to slow/booth, after the generic synthesis. That means, even if you might set the user_speed_grade, the RTL Compiler will change the sub-architecture selection during technology mapping time. In other words, if you had tighter constraints, you would probably not have been Booth architecture, either...

    In your technology/constraints it is possible. In my technology/constraints, not.

    I will relax my timing closure now and will see whether it will cheat RTL Compiler to infer fast synthetic operator as Booth multiplier...


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Nov 20 2007 10:18 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Grasshopper,

    i have found the reason. The reason is the script I am using is setting input_pragma_keyword attribute a value other than default setting, which does not include the string "cadence" any more. Therefore RTL Compiler does not recognize the cadence inline pragma any more.

    When I keep the attribute input_pragma_keyword in its default value, I get Booth architecture, because RTL Compiler recognizes inline pragma keyword "cadence".

    When I change the value of this attribute in such a way that its value does not include string "cadence", RTL Compiler is unable to recognize the inline pragma keyword "cadence" and thus it does not infer Booth operator.

    But I will contact Cadence to tell them that neither read_hdl nor elaborate produces any message saying that it recognized the inline pragma in the default value of the said attribute.


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Nov 20 2007 10:38 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    I doubt much can be done. Once you change the default it simply looks like a comment so I cannot imagine the tool doing anything about it.

    gh-


    Originally posted in cdnusers.org by grasshopper
    • Post Points: 0
  • Tue, Nov 20 2007 11:19 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    Grasshopper,

    thank you very much for your kind help. The setting of the said attribute is used only for inline pragmas. But despite that I can achieve the same effect by setting user_sub_arch to booth for all synthetic operators implied for multipliers [find / -subdesign mult*signed*].

    However this is not explicitly stated in Cadence documents. Cadence documents do not tell me that I have to set architecture selection of these synthetic operators. Instead, the document tells me that I just need to set the attribute to the module.

    When RTL Compiler sees an arithmetic operation during elaboration time, it infers syntetic operators. However the names of these operators (inferred submodules) are unknown by the user during elaboration time.

    Therefore the user only can know the name of the module in which the multiplier is implied, nothing more. In my case above it is "mult_kernel". Then you might think it must be OK to set the multiplier architecture for the said module (done after elaboration):

    rc:/> set_attr user_sub_arch booth [find / -subdesign mult_kern*]
    Setting attribute of subdesign 'mult_kernel_WIDTH_A5_WIDTH_B10': 'user_sub_arch' = booth

    However, when you look at the design, synthetic operator will not take Booth architecture selection.

    rc:/> foreach item [find / -subdesign *] { puts "[basename $item] -> [get_attr user_sub_arch $item]" }
    mult_kernel_WIDTH_A5_WIDTH_B10 -> booth
    mult_unsigned ->
    mux ->
    mux_59 ->
    mux_78 ->

    rc:/> foreach item [find / -subdesign *] { puts "[basename $item] -> [get_attr sub_arch $item]" }
    mult_kernel_WIDTH_A5_WIDTH_B10 -> booth
    mult_unsigned -> non_booth
    mux ->
    mux_59 ->
    mux_78 ->
    rc:/>

    Therefore the architecture will never be Booth.


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Sat, Mar 8 2008 1:06 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,910
    RE: sub architecture selection Reply

    To my point "name of synthetic operators are unknown by user during runtime":

    This behaviour can be controlled by gen_module_prefix attribute. If we set this attribute before elaboration, then the synthetic operators generated during elaboration time will have this prefix. Very good.

    The side effect of this attribute is that any uniquification will take this prefix, too. Therefore to identify operators in your uniquified design for debugging purposes, this attribute (gen_module_prefix) must be set some other value right before any uniquificaton.


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
Page 1 of 1 (14 items)
Sort Posts:
Started by archive at 20 Jan 2007 09:54 AM. Topic has 13 replies.