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 Clock networks in RC 

Last post Fri, Dec 29 2006 10:45 AM by archive. 1 replies.
Started by archive 29 Dec 2006 10:45 AM. Topic has 1 replies and 1059 views
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  • Fri, Dec 29 2006 10:45 AM

    • archive
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    Clock networks in RC Reply

    Hi.
    This question is related to myazdani's question.
    I'm looking for the equivalent command of DC's "set_ideal_network" especially in connection to clock networks - as far as considering the literature, I've understood clock networks are automatically treated as ideal so I have few questions I'd be happy to get an answer on:
    1. Is what I wrote correct - are clock networks automatically treated by RC as ideal?
    2. How can I manually set and unset this property on any net I desire? I haven't been able to find the answer in the manual.

    Thank You,
    Adi.


    Originally posted in cdnusers.org by adi_j
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  • Wed, Jan 17 2007 3:48 PM

    • archive
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    RE: Clock networks in RC Reply


    1) Yes, clock networks are ideal by default.

    2) I think you want to set the ideal_network attribute, or do set it with SDC. See the RTL Compiler
    Attribute Reference Manual

    ideal_network
    ideal_network {true | false}
    Default: false
    Read-write attribute. Sets the network of the specified driver pin to an ideal network. The pin
    must be a driving pin. This attribute propagates through combinational gates, latches, and
    hierarchical boundaries, unlike the ideal_driver attribute.....etc.


    Originally posted in cdnusers.org by galaxy_jason
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Started by archive at 29 Dec 2006 10:45 AM. Topic has 1 replies.