Home > Community > Forums > Logic Design > simplify_constants

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 simplify_constants 

Last post Tue, Dec 12 2006 4:26 AM by archive. 1 replies.
Started by archive 12 Dec 2006 04:26 AM. Topic has 1 replies and 976 views
Page 1 of 1 (2 items)
Sort Posts:
  • Tue, Dec 12 2006 4:26 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    simplify_constants Reply

    is there any command/combination of commands in RC which serve for simplify_constants in DC?


    Originally posted in cdnusers.org by sporadic crash
    • Post Points: 0
  • Tue, Dec 12 2006 8:14 AM

    • archive
    • Top 75 Contributor
    • Joined on Fri, Jul 4 2008
    • Posts 88
    • Points 4,930
    RE: simplify_constants Reply

    Hi,
    By default, RTL Compiler performs boundary optimization during synthesis for all hierarchical instances in the design. To preserve the input and output pins of a subdesign, you can turn off the boundary optimization.

    set_attr boundary_opto false [find / -subdesign $subdsgn]


    Originally posted in cdnusers.org by Stalker
    • Post Points: 0
Page 1 of 1 (2 items)
Sort Posts:
Started by archive at 12 Dec 2006 04:26 AM. Topic has 1 replies.