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 constraining between ports and clock domain 

Last post Mon, Dec 11 2006 11:31 AM by archive. 19 replies.
Started by archive 11 Dec 2006 11:31 AM. Topic has 19 replies and 5197 views
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  • Mon, Dec 11 2006 11:31 AM

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    constraining between ports and clock domain Reply

    I have a clock named "clk_design". How canĀ I constrain all paths between input ports and this clock?

    I have applied following:

    define_cost_group input_to_clk_design
    path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path

    But when I apply report timing -cost_group input_to_clk_design, report tells me that no path group has been found.

    Any ideas? What shall i give as -to option for path_group?



    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 11:48 AM

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    RE: constraining between ports and clock domain Reply

    Clock object is a valid object of the -to option. Look at the 'exceptions' attribute of the cost group to see if any path group exist. If the path_group does exist, look at the 'paths' attribute of the path_group to see if there is any path.


    Originally posted in cdnusers.org by synthman
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  • Mon, Dec 11 2006 12:05 PM

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    RE: constraining between ports and clock domain Reply

    The cost group is not a constraint it is a grouping mechanism to direct the optimization and facilitate reporting.

    Here are a few things you may want to make check

    - Do you have an input delay define on your input port?
    - If you run report timing -from do you get a path to the clk_design clock reported?
    - Do you have any false path from input to that clock (sometime used when only working on FF to FF paths)
    - Do you have any path_group command which might move those path to a different group?
    for example if you input delay use clk_design and you have a path_group -from clk_design -to clk_design you will also have your input to clk_design in that group.

    Thanks,
    Eric.


    Originally posted in cdnusers.org by evenditti
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  • Mon, Dec 11 2006 12:10 PM

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    RE: constraining between ports and clock domain Reply

    I see following:

    - cost_group input_to_clk_design exists

    [b]rc:/> ls -attribute /designs/*/cost_groups/input_to_clk_design[/b]
    /designs//timing/cost_groups/input_to_clk_design (cost_group)
    Attributes:
    exceptions = /designs//timing/exceptions/path_groups/input_to_clk_design_path

    [b]rc:/> ls -attribute /designs/*/exceptions/path_groups/input_to_clk_design_path[/b]
    /designs//timing/exceptions/path_groups/input_to_clk_design_path (exception)
    Attributes:
    cost_group = /designs//timing/cost_groups/input_to_clk_design
    domain =
    exception_type = path_group
    from_points = /designs//ports_in/...
    paths = specify_paths -from {/designs//ports_in* ...
    priority = 90
    to_points = /designs//timing/clock_domains/domain_1/clk_design
    rc:/>

    Now report timing -cost_group input_2_clk_design


    Shall I define the clock with "domain"?


    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 12:12 PM

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    RE: constraining between ports and clock domain Reply

    The last sentence in the previous posting is incomplete:

    [b]report timing -cost_group input_to_clk_design[/b]

    gives me

    no paths found.


    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 12:17 PM

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    RE: constraining between ports and clock domain Reply

    if you pick one of the input port and do report timing -from input_port_name, what do you get?


    Originally posted in cdnusers.org by evenditti
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  • Mon, Dec 11 2006 12:24 PM

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    RE: constraining between ports and clock domain Reply


    report timing -from /designs//ports_in/

    Exception : 'path_disables/_line_2563'
    Timing slack : UNCONSTRAINED
    Start-point :
    End-point :

    (u) : Net has unmapped pin(s).

    It seems it is still unconstrained.

    I have used following commands:
    1. create_clock -period $period -waveform [ list $rise $fall ] [ get_ports {clk_design} ] -domain clk_design
    2. define_cost_group -name input_to_clk_design
    3. path_group -from /designs/*/ports_in/* -to clk_design -group input_to_clk_design -name input_to_clk_design_path

    report timing -cost_group input_to_clk_design

    tells me no path found.



    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 12:30 PM

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    RE: constraining between ports and clock domain Reply

    What version of RC do you use? Do you have any path from input ports that goes to registers clocked by clock clk_design? Try this command to see where the input port fanouts to:

    fanout -end


    Originally posted in cdnusers.org by synthman
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  • Mon, Dec 11 2006 12:34 PM

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    RE: constraining between ports and clock domain Reply

    yes definitely I have. I have implemented this design :)

    fanout -end

    gives me a long list!

    What am I missing here??? It must be simple..
    1. create_clock
    2. define_cost_group
    3. path_group

    What else? What am I doing wrong?

    RC is 6.1.


    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 12:38 PM

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    RE: constraining between ports and clock domain Reply

    You need to define input delay with external_delay command. If you don't have that, report timing will show the path as unconstrained, but it would show the path from input to register.

    Try to report timing from register to register, if it shows no path, then it might be something wrong with the library.


    Originally posted in cdnusers.org by synthman
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  • Mon, Dec 11 2006 12:46 PM

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    RE: constraining between ports and clock domain Reply

    external_delay helped.

    I did not do it. Instead, I applied "dc::set_input_delay" to an external pin.
    It is not enough, it seems so. What you think?


    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 12:51 PM

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    RE: constraining between ports and clock domain Reply

    dc::set_input_delay should work, how do you apply it?


    Originally posted in cdnusers.org by synthman
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  • Mon, Dec 11 2006 12:54 PM

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    RE: constraining between ports and clock domain Reply

    set_input_delay $delay -clock clk_designl $inputs

    it is called from an SDC file. I have written in the previous posting to imply that I have used an SDC style, not RC style.

    Am I missing anything here?


    Originally posted in cdnusers.org by sporadic crash
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  • Mon, Dec 11 2006 12:59 PM

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    RE: constraining between ports and clock domain Reply

    In your previous email you wrote

    1. create_clock
    2. define_cost_group
    3. path_group

    You need to read the sdc between 1 and 2. not before 1 or after 3.

    Eric.


    Originally posted in cdnusers.org by evenditti
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  • Mon, Dec 11 2006 1:02 PM

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    RE: constraining between ports and clock domain Reply

    1. create_clock is in an SDC file, called by another TCL script, using "read_sdc".
    2. and 3. are in the TCL script, after the read_sdc call.

    after external_delay, I have applied dc::set_input_delay again, RC tells me that external_delay is removed.
    Are both commands equivalent, ie. "dc::set_input_delay" and "external_delay"?



    Originally posted in cdnusers.org by sporadic crash
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Started by archive at 11 Dec 2006 11:31 AM. Topic has 19 replies.